From: Dylan Jhong <dylan@andestech.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Alan Quey-Liang Kao\(\(\(\(\(\(\(\(\(\(\)"
<alankao@andestech.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Ruinland Chuan-Tzu Tsa\(\(\(\(\(\(\(\(\(\(\)"
<ruinland@andestech.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH 1/3] Andes RISC-V PLIC
Date: Thu, 11 Mar 2021 14:52:15 +0800 [thread overview]
Message-ID: <20210311065215.GB469@atcfdc88> (raw)
In-Reply-To: <CAEUhbmVgQzzS4DSOKM_zBxMMAb0bCZBJOZfQ7BUop84SaikZxg@mail.gmail.com>
On Wed, Mar 10, 2021 at 02:05:51PM +0800, Bin Meng wrote:
> On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong <dylan@andestech.com> wrote:
> >
> > Andes PLIC (Platform-Level Interrupt Controller) device provides an
> > interrupt controller functionality based on Andes's PLIC specification.
> >
> > The Andes PLIC can handle either external interrupts (PLIC)
> > or interprocessor interrupts (PLICSW).
> >
> > While Andes PLIC spec includes vector interrupt and interrupt preemption,
> > we leave them as future items for now.
> >
> > Signed-off-by: Dylan Jhong <dylan@andestech.com>
> > Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> > ---
> > hw/intc/Kconfig | 3 +
> > hw/intc/andes_plic.c | 505 +++++++++++++++++++++++++++++++++++
> > hw/intc/meson.build | 1 +
> > include/hw/intc/andes_plic.h | 130 +++++++++
> > 4 files changed, 639 insertions(+)
> > create mode 100644 hw/intc/andes_plic.c
> > create mode 100644 include/hw/intc/andes_plic.h
>
> Is the Andes PLIC spec public available?
>
Please refer to Andes website
http://www.andestech.com/en/products-solutions/product-documentation/
> What's the difference between Andres's implementation and the SiFive's?
>
Currently, the Andes's PLIC specification allows the following functions:
Preemptive Priority Interrupt, Vectored Mode Interrupt Dispatching and
Software-Generated Interrupt.
In this patch, we only implement "Software-Generated Interrupt" feature.
For the other PLIC features, we'll leave them as future items for now.
> Regards,
> Bin
next prev parent reply other threads:[~2021-03-11 6:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 3:33 [PATCH 0/3] Support Andes AE350 Platform Dylan Jhong
2021-03-10 3:33 ` [PATCH 1/3] Andes RISC-V PLIC Dylan Jhong
2021-03-10 6:05 ` Bin Meng
2021-03-11 6:52 ` Dylan Jhong [this message]
2021-03-10 7:50 ` Yixun Lan
2021-03-11 15:42 ` Alistair Francis
2021-03-10 3:33 ` [PATCH 2/3] Andes RISC-V PLMT Dylan Jhong
2021-03-10 3:33 ` [PATCH 3/3] Andes AE350 RISC-V Machine Dylan Jhong
2021-03-10 6:15 ` Bin Meng
2021-03-11 6:50 ` Dylan Jhong
2021-03-11 15:46 ` Alistair Francis
2021-03-12 1:07 ` Bin Meng
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