From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org
Subject: [PATCH v5 05/57] tcg/tci: Split out tci_args_rrr
Date: Thu, 11 Mar 2021 08:39:06 -0600 [thread overview]
Message-ID: <20210311143958.562625-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210311143958.562625-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 154 ++++++++++++++++++++----------------------------------
1 file changed, 57 insertions(+), 97 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index e5aba3a9fa..1c879a2536 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr,
*r1 = tci_read_r(tb_ptr);
}
+static void tci_args_rrr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
@@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
- TCGReg r0, r1;
+ TCGReg r0, r1, r2;
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
@@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (mixed 32/64 bit). */
CASE_32_64(add)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 + t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] + regs[r2];
break;
CASE_32_64(sub)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 - t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] - regs[r2];
break;
CASE_32_64(mul)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 * t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] * regs[r2];
break;
CASE_32_64(and)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 & t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] & regs[r2];
break;
CASE_32_64(or)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 | t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 ^ t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] ^ regs[r2];
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_div_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
break;
case INDEX_op_divu_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
break;
case INDEX_op_rem_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
break;
case INDEX_op_remu_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
break;
case INDEX_op_shr_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
break;
case INDEX_op_sar_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, rol32(t1, t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = rol32(regs[r1], regs[r2] & 31);
break;
case INDEX_op_rotr_i32:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ror32(t1, t2 & 31));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = ror32(regs[r1], regs[r2] & 31);
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
@@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */
case INDEX_op_div_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
break;
case INDEX_op_divu_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
break;
case INDEX_op_rem_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
break;
case INDEX_op_remu_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 << (t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1 >> (t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = regs[r1] >> (regs[r2] & 63);
break;
case INDEX_op_sar_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, rol64(t1, t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- t2 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ror64(t1, t2 & 63));
+ tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
+ regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
--
2.25.1
next prev parent reply other threads:[~2021-03-11 14:42 UTC|newest]
Thread overview: 107+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 14:39 [PATCH v5 00/57] TCI fixes and cleanups Richard Henderson
2021-03-11 14:39 ` [PATCH v5 01/57] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-03-11 16:05 ` Stefan Weil
2021-03-11 14:39 ` [PATCH v5 02/57] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-03-16 22:46 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 03/57] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-03-16 22:50 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 04/57] tcg/tci: Split out tci_args_rr Richard Henderson
2021-03-16 22:51 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` Richard Henderson [this message]
2021-03-16 22:53 ` [PATCH v5 05/57] tcg/tci: Split out tci_args_rrr Philippe Mathieu-Daudé
2021-03-17 3:38 ` Richard Henderson
2021-03-11 14:39 ` [PATCH v5 06/57] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-03-16 22:55 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 07/57] tcg/tci: Split out tci_args_l Richard Henderson
2021-03-16 22:56 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 08/57] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-03-16 22:58 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 09/57] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-03-16 23:00 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 10/57] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-03-16 23:52 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 11/57] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-03-16 23:04 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 12/57] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-03-16 23:05 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 13/57] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-03-17 0:28 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 14/57] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-03-16 23:07 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 15/57] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-03-16 23:46 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 16/57] tcg/tci: Clean up deposit operations Richard Henderson
2021-03-17 0:32 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 17/57] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-03-16 23:10 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 18/57] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-16 23:14 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 19/57] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-03-16 22:23 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 20/57] tcg/tci: Remove tci_disas Richard Henderson
2021-03-16 22:24 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 21/57] tcg/tci: Implement the disassembler properly Richard Henderson
2021-03-17 0:38 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 22/57] tcg: Build ffi data structures for helpers Richard Henderson
2021-03-16 22:35 ` Philippe Mathieu-Daudé
2021-03-17 3:51 ` Richard Henderson
2021-03-11 14:39 ` [PATCH v5 23/57] tcg/tci: Use ffi for calls Richard Henderson
2021-03-11 14:39 ` [PATCH v5 24/57] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-03-11 14:39 ` [PATCH v5 25/57] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-03-11 14:39 ` [PATCH v5 26/57] tcg/tci: Push opcode emit into each case Richard Henderson
2021-03-16 22:39 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 27/57] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-03-17 15:03 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 28/57] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-03-16 23:17 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 29/57] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-03-16 23:18 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 30/57] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-03-16 23:45 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 31/57] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-03-16 23:27 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 32/57] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-03-16 23:27 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 33/57] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-03-16 23:28 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 34/57] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-03-16 23:29 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 35/57] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-03-16 23:30 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 36/57] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-03-16 23:30 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 37/57] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-03-16 23:31 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 38/57] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-03-16 23:31 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 39/57] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-16 23:43 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 40/57] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-03-16 23:41 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 41/57] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-03-16 23:33 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 42/57] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-03-16 23:39 ` Philippe Mathieu-Daudé
2021-03-17 3:59 ` Richard Henderson
2021-03-17 17:15 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 43/57] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-03-11 14:39 ` [PATCH v5 44/57] tcg/tci: Emit setcond before brcond Richard Henderson
2021-03-11 14:39 ` [PATCH v5 45/57] tcg/tci: Remove tci_write_reg Richard Henderson
2021-03-11 14:39 ` [PATCH v5 46/57] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-03-11 14:39 ` [PATCH v5 47/57] tcg/tci: Implement goto_ptr Richard Henderson
2021-03-11 14:39 ` [PATCH v5 48/57] tcg/tci: Implement movcond Richard Henderson
2021-03-11 14:39 ` [PATCH v5 49/57] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-03-11 14:39 ` [PATCH v5 50/57] tcg/tci: Implement extract, sextract Richard Henderson
2021-03-11 14:39 ` [PATCH v5 51/57] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-03-11 14:39 ` [PATCH v5 52/57] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-03-16 22:44 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 53/57] tcg/tci: Implement add2, sub2 Richard Henderson
2021-03-11 14:39 ` [PATCH v5 54/57] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-03-11 14:39 ` [PATCH v5 55/57] tests/tcg: Increase timeout for TCI Richard Henderson
2021-03-11 14:39 ` [PATCH v5 56/57] gitlab: Rename ACCEL_CONFIGURE_OPTS to EXTRA_CONFIGURE_OPTS Richard Henderson
2021-05-27 15:56 ` Philippe Mathieu-Daudé
2021-03-11 14:39 ` [PATCH v5 57/57] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-05-27 15:57 ` Philippe Mathieu-Daudé
2021-03-11 15:28 ` [PATCH v5 00/57] TCI fixes and cleanups no-reply
2021-03-17 0:23 ` Philippe Mathieu-Daudé
2021-03-17 0:41 ` Philippe Mathieu-Daudé
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as well as URLs for NNTP newsgroup(s).