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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id a5sm8254544wrs.35.2021.03.12.08.24.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 08:24:41 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 1/5] target/mips/tx79: Introduce LQ opcode (Load Quadword) Date: Fri, 12 Mar 2021 17:24:30 +0100 Message-Id: <20210312162434.1869129-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210312162434.1869129-1-f4bug@amsat.org> References: <20210312162434.1869129-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , "Maciej W . Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 8 ++++++++ target/mips/translate.c | 16 ++-------------- target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 14 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0f748b53a64..f1f17470a00 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -13,6 +13,8 @@ &rtype rs rt rd sa +&itype base rt offset + ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. @@ -22,6 +24,8 @@ @rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 +@ldst ...... base:5 rt:5 offset:16 &itype + ########################################################################### MFHI1 011100 0000000000 ..... 00000 010000 @rd @@ -37,3 +41,7 @@ PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd + +# SPECIAL + +LQ 011110 ..... ..... ................ @ldst diff --git a/target/mips/translate.c b/target/mips/translate.c index c518bf3963b..c822083f031 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1167,7 +1167,6 @@ enum { enum { MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */ MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; @@ -24429,11 +24428,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) } } -static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ -} - static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ @@ -25332,14 +25326,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MDMX: /* MMI_OPC_LQ */ - if (ctx->insn_flags & INSN_R5900) { -#if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); -#endif - } else { - /* MDMX: Not implemented. */ - } + case OPC_MDMX: + /* MDMX: Not implemented. */ break; case OPC_PCREL: check_insn(ctx, ISA_MIPS_R6); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index ad83774b977..b5a9eb3de76 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -177,6 +177,41 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * SQ rt, offset(base) Store Quadword */ +static bool trans_LQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0; + TCGv addr; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new_i64(); + addr = tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower half */ + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr(t0, a->rt); + + /* Upper half */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr_hi(t0, a->rt); + + tcg_temp_free(t0); + tcg_temp_free(addr); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- -- 2.26.2