From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 02/38] tcg/tci: Rename tci_read_r to tci_read_rval
Date: Wed, 17 Mar 2021 09:34:08 -0600 [thread overview]
Message-ID: <20210317153444.310566-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org>
In the next patches, we want to use tci_read_r to return
the raw register number. So rename the existing function,
which returns the register value, to tci_read_rval.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 192 +++++++++++++++++++++++++++---------------------------
1 file changed, 96 insertions(+), 96 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 6a0bdf028b..6d6a5510da 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr)
/* Read indexed register (native size) from bytecode. */
static tcg_target_ulong
-tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
+tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{
tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
*tb_ptr += 1;
@@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- uint32_t low = tci_read_r(regs, tb_ptr);
- return tci_uint64(tci_read_r(regs, tb_ptr), low);
+ uint32_t low = tci_read_rval(regs, tb_ptr);
+ return tci_uint64(tci_read_rval(regs, tb_ptr), low);
}
#elif TCG_TARGET_REG_BITS == 64
/* Read indexed register (64 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
- return tci_read_r(regs, tb_ptr);
+ return tci_read_rval(regs, tb_ptr);
}
#endif
@@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
static target_ulong
tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{
- target_ulong taddr = tci_read_r(regs, tb_ptr);
+ target_ulong taddr = tci_read_rval(regs, tb_ptr);
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
- taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32;
+ taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32;
#endif
return taddr;
}
@@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue;
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break;
@@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break;
#endif
CASE_32_64(mov)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1);
break;
case INDEX_op_tci_movi_i32:
@@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(ld8u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break;
CASE_32_64(ld8s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break;
CASE_32_64(ld16u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break;
CASE_32_64(ld16s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
break;
case INDEX_op_ld_i32:
CASE_64(ld32u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break;
CASE_32_64(st8)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
CASE_32_64(st16)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
CASE_64(st32)
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
break;
@@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(add)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
break;
CASE_32_64(sub)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
break;
CASE_32_64(mul)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
CASE_32_64(and)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
break;
CASE_32_64(or)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
break;
CASE_32_64(xor)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
break;
@@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break;
@@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
@@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i32:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
@@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mulu2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
- t2 = tci_read_r(regs, &tb_ptr);
- tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
+ tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1);
break;
#endif
@@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st_i64:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint64_t *)(t1 + t2) = t0;
break;
@@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
@@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
- t2 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
+ t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_r(regs, &tb_ptr);
- t1 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
@@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1);
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1);
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
- t1 = tci_read_r(regs, &tb_ptr);
+ t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap64(t1));
break;
#endif
@@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
break;
case INDEX_op_qemu_st_i32:
- t0 = tci_read_r(regs, &tb_ptr);
+ t0 = tci_read_rval(regs, &tb_ptr);
taddr = tci_read_ulong(regs, &tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
--
2.25.1
next prev parent reply other threads:[~2021-03-17 15:53 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 15:34 [PULL 00/38] tcg patch queue for 6.0 Richard Henderson
2021-03-17 15:34 ` [PULL 01/38] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-03-17 15:34 ` Richard Henderson [this message]
2021-03-17 15:34 ` [PULL 03/38] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-03-17 15:34 ` [PULL 04/38] tcg/tci: Split out tci_args_rr Richard Henderson
2021-03-17 15:34 ` [PULL 05/38] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-03-17 15:34 ` [PULL 06/38] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-03-17 15:34 ` [PULL 07/38] tcg/tci: Split out tci_args_l Richard Henderson
2021-03-17 15:34 ` [PULL 08/38] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-03-17 15:34 ` [PULL 09/38] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-03-17 15:34 ` [PULL 10/38] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-03-17 15:34 ` [PULL 11/38] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-03-17 15:34 ` [PULL 12/38] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-03-17 15:34 ` [PULL 13/38] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-03-17 15:34 ` [PULL 14/38] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-03-17 15:34 ` [PULL 15/38] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-03-17 15:34 ` [PULL 16/38] tcg/tci: Clean up deposit operations Richard Henderson
2021-03-17 15:34 ` [PULL 17/38] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-03-17 15:34 ` [PULL 18/38] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-17 15:34 ` [PULL 19/38] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-03-17 15:34 ` [PULL 20/38] tcg/tci: Remove tci_disas Richard Henderson
2021-03-17 15:34 ` [PULL 21/38] tcg/tci: Implement the disassembler properly Richard Henderson
2021-05-15 10:57 ` Philippe Mathieu-Daudé
2021-05-16 1:08 ` Richard Henderson
2021-03-17 15:34 ` [PULL 22/38] tcg/tci: Push opcode emit into each case Richard Henderson
2021-03-17 15:34 ` [PULL 23/38] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-03-17 15:34 ` [PULL 24/38] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-03-17 15:34 ` [PULL 25/38] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-03-17 15:34 ` [PULL 26/38] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-03-17 15:34 ` [PULL 27/38] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-03-17 15:34 ` [PULL 28/38] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-03-17 15:34 ` [PULL 29/38] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-03-17 15:34 ` [PULL 30/38] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-03-17 15:34 ` [PULL 31/38] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-03-17 15:34 ` [PULL 32/38] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-03-17 15:34 ` [PULL 33/38] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-03-17 15:34 ` [PULL 34/38] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-03-17 15:34 ` [PULL 35/38] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-17 15:34 ` [PULL 36/38] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-03-17 15:34 ` [PULL 37/38] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-03-17 15:34 ` [PULL 38/38] tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op Richard Henderson
2021-03-18 19:00 ` [PULL 00/38] tcg patch queue for 6.0 Peter Maydell
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