From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Miroslav Rezanina <mrezanin@redhat.com>
Subject: [PULL 38/38] tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op
Date: Wed, 17 Mar 2021 09:34:44 -0600 [thread overview]
Message-ID: <20210317153444.310566-39-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210317153444.310566-1-richard.henderson@linaro.org>
From: Miroslav Rezanina <mrezanin@redhat.com>
There are two different versions of prototype for tcg_out_op and
tcg_out_vec_op functions:
1) using const TCGArg *args and const int *const_args arguments
2) using const TCGArg args[TCG_MAX_OP_ARGS] and const int
const_args[TCG_MAX_OP_ARGS] aguments.
This duality causes warnings on GCC 11 and prevents build using
--enable-werror. As second version provides more information,
unify functions prototypes to this variant.
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
Message-Id: <20210312121418.139093-1-mrezanin@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 19 +++++++++++--------
tcg/aarch64/tcg-target.c.inc | 3 ++-
tcg/i386/tcg-target.c.inc | 6 ++++--
tcg/mips/tcg-target.c.inc | 3 ++-
tcg/ppc/tcg-target.c.inc | 8 +++++---
tcg/riscv/tcg-target.c.inc | 3 ++-
tcg/s390/tcg-target.c.inc | 3 ++-
tcg/tci/tcg-target.c.inc | 5 +++--
8 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 2991112829..de91bb6e9e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -107,8 +107,9 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg);
-static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args);
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS]);
#if TCG_TARGET_MAYBE_vec
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src);
@@ -116,9 +117,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg base, intptr_t offset);
static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, int64_t arg);
-static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
- unsigned vece, const TCGArg *args,
- const int *const_args);
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS]);
#else
static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src)
@@ -135,9 +137,10 @@ static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
{
g_assert_not_reached();
}
-static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
- unsigned vece, const TCGArg *args,
- const int *const_args)
+static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
g_assert_not_reached();
}
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index fcaa5aface..f07ba98aa4 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2286,7 +2286,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
static const AArch64Insn cmp_vec_insn[16] = {
[TCG_COND_EQ] = I3616_CMEQ,
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 40326c2806..415c5c0796 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2177,7 +2177,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
}
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
int c, const_a2, vexop, rexw = 0;
@@ -2613,7 +2614,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
static int const add_insn[4] = {
OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index ab55f3109b..8738a3a581 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1651,7 +1651,8 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
}
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
MIPSInsn i1, i2;
TCGArg a0, a1, a2;
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 4377d15d62..838ccfa42d 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2319,8 +2319,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out32(s, BCLR | BO_ALWAYS);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args)
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
int c;
@@ -3115,7 +3116,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
unsigned vecl, unsigned vece,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
static const uint32_t
add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index e700c52067..ef43147040 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1212,7 +1212,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
static const tcg_insn_unit *tb_ret_addr;
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0 = args[0];
TCGArg a1 = args[1];
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 695d7ee652..af8dfe81ac 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1705,7 +1705,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
case glue(glue(INDEX_op_,x),_i64)
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
S390Opcode op, op2;
TCGArg a0, a1, a2;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 7e7b9fed44..ee6cdfec71 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -613,8 +613,9 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
# define CASE_64(x)
#endif
-static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args)
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
switch (opc) {
case INDEX_op_exit_tb:
--
2.25.1
next prev parent reply other threads:[~2021-03-17 16:19 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 15:34 [PULL 00/38] tcg patch queue for 6.0 Richard Henderson
2021-03-17 15:34 ` [PULL 01/38] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-03-17 15:34 ` [PULL 02/38] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-03-17 15:34 ` [PULL 03/38] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-03-17 15:34 ` [PULL 04/38] tcg/tci: Split out tci_args_rr Richard Henderson
2021-03-17 15:34 ` [PULL 05/38] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-03-17 15:34 ` [PULL 06/38] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-03-17 15:34 ` [PULL 07/38] tcg/tci: Split out tci_args_l Richard Henderson
2021-03-17 15:34 ` [PULL 08/38] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-03-17 15:34 ` [PULL 09/38] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-03-17 15:34 ` [PULL 10/38] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-03-17 15:34 ` [PULL 11/38] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-03-17 15:34 ` [PULL 12/38] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-03-17 15:34 ` [PULL 13/38] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-03-17 15:34 ` [PULL 14/38] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-03-17 15:34 ` [PULL 15/38] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-03-17 15:34 ` [PULL 16/38] tcg/tci: Clean up deposit operations Richard Henderson
2021-03-17 15:34 ` [PULL 17/38] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-03-17 15:34 ` [PULL 18/38] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-17 15:34 ` [PULL 19/38] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-03-17 15:34 ` [PULL 20/38] tcg/tci: Remove tci_disas Richard Henderson
2021-03-17 15:34 ` [PULL 21/38] tcg/tci: Implement the disassembler properly Richard Henderson
2021-05-15 10:57 ` Philippe Mathieu-Daudé
2021-05-16 1:08 ` Richard Henderson
2021-03-17 15:34 ` [PULL 22/38] tcg/tci: Push opcode emit into each case Richard Henderson
2021-03-17 15:34 ` [PULL 23/38] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-03-17 15:34 ` [PULL 24/38] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-03-17 15:34 ` [PULL 25/38] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-03-17 15:34 ` [PULL 26/38] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-03-17 15:34 ` [PULL 27/38] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-03-17 15:34 ` [PULL 28/38] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-03-17 15:34 ` [PULL 29/38] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-03-17 15:34 ` [PULL 30/38] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-03-17 15:34 ` [PULL 31/38] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-03-17 15:34 ` [PULL 32/38] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-03-17 15:34 ` [PULL 33/38] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-03-17 15:34 ` [PULL 34/38] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-03-17 15:34 ` [PULL 35/38] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-03-17 15:34 ` [PULL 36/38] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-03-17 15:34 ` [PULL 37/38] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-03-17 15:34 ` Richard Henderson [this message]
2021-03-18 19:00 ` [PULL 00/38] tcg patch queue for 6.0 Peter Maydell
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