From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 987E0C433C1 for ; Fri, 26 Mar 2021 10:20:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7055061A18 for ; Fri, 26 Mar 2021 10:20:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7055061A18 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:37120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lPjaI-0000pX-5k for qemu-devel@archiver.kernel.org; Fri, 26 Mar 2021 06:20:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPjZK-0008Hs-Oa; Fri, 26 Mar 2021 06:19:55 -0400 Received: from exmail.andestech.com ([60.248.187.195]:31465 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPjZ4-0008Am-FO; Fri, 26 Mar 2021 06:19:52 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 12QAIWk1001833; Fri, 26 Mar 2021 18:18:32 +0800 (GMT-8) (envelope-from dylan@andestech.com) Received: from andestech.com (10.0.15.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 26 Mar 2021 18:18:32 +0800 Date: Fri, 26 Mar 2021 18:18:33 +0800 From: Dylan Jhong To: Alistair Francis Subject: Re: [PATCH V3] target/riscv: Align the data type of reset vector address Message-ID: <20210326101833.GA21700@andestech.com> References: <20210325094150.28918-1-dylan@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.0.15.65] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 12QAIWk1001833 Received-SPF: pass client-ip=60.248.187.195; envelope-from=dylan@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Alan Quey-Liang =?utf-8?B?S2FvKOmrmOmtgeiJryk=?= , Sagar Karandikar , Bastian Koppelmann , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , "x5710999x@gmail.com" , Ruinland Chuan-Tzu =?utf-8?B?VHNhKOiUoeWCs+izhyk=?= , Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Mar 26, 2021 at 04:19:09AM +0800, Alistair Francis wrote: > On Thu, Mar 25, 2021 at 5:43 AM Dylan Jhong wrote: > > > > Signed-off-by: Dylan Jhong > > Signed-off-by: Ruinland ChuanTzu Tsai > > --- > > target/riscv/cpu.c | 6 +++++- > > target/riscv/cpu.h | 2 +- > > 2 files changed, 6 insertions(+), 2 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7d6ed80f6b..8a5f18bcb0 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature) > > env->features |= (1ULL << feature); > > } > > > > -static void set_resetvec(CPURISCVState *env, int resetvec) > > +static void set_resetvec(CPURISCVState *env, target_ulong resetvec) > > { > > #ifndef CONFIG_USER_ONLY > > env->resetvec = resetvec; > > @@ -554,7 +554,11 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > > +#if defined(TARGET_RISCV32) > > + DEFINE_PROP_UINT32("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > > +#elif defined(TARGET_RISCV64) > > DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > > +#endif > > Thanks for the patch! > > I don't want to introduce any more define(TARGET_* macros as we are > trying to make RISC-V QEMU xlen independent. > > The hexagon port has an example of how you can use target_ulong here: > > DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, > 0, qdev_prop_uint32, target_ulong); > > can you do something like that instead? > > Alistair > Hi Alistair, Thanks for the comments. But so far I did not see a way to satisfy both 32/64bit reset vector define. The problem occurs in the 5th parameter of DEFINE_PROP_UNSIGNED(_name, _state, _field, _defval, _prop, _type). We need to specify the _prop parameter to one of the PropertyInfo struct as shown below: extern const PropertyInfo qdev_prop_bit; extern const PropertyInfo qdev_prop_bit64; extern const PropertyInfo qdev_prop_bool; extern const PropertyInfo qdev_prop_enum; extern const PropertyInfo qdev_prop_uint8; extern const PropertyInfo qdev_prop_uint16; extern const PropertyInfo qdev_prop_uint32; extern const PropertyInfo qdev_prop_int32; extern const PropertyInfo qdev_prop_uint64; extern const PropertyInfo qdev_prop_int64; extern const PropertyInfo qdev_prop_size; extern const PropertyInfo qdev_prop_string; extern const PropertyInfo qdev_prop_on_off_auto; extern const PropertyInfo qdev_prop_size32; extern const PropertyInfo qdev_prop_arraylen; extern const PropertyInfo qdev_prop_link; Currently, there is no structure like "qdev_prop_target_ulong". So, we still need to use an if-else condition to determine the attributes of the 5th parameter. Something like this: #if defined(TARGET_RISCV32) DEFINE_PROP_UNSIGNED("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC, qdev_prop_uint32 target_ulong), #elif defined(TARGET_RISCV64) DEFINE_PROP_UNSIGNED("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC, qdev_prop_uint64 target_ulong), #endif I think this is not be what you meant. The other architectures seem to ignore this, they just choose one of the attributes(qdev_prop_uint32/64) as their parameter. So now we have 2 options: 1. Use "qdev_prop_uint64" as the 5th parameter DEFINE_PROP_UNSIGNED("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC, qdev_prop_uint64 target_ulong), 2. Use if-else condition [patch v3] Or if you have other opinions, please bring them up and discuss them together. Thanks, Dylan > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 0a33d387ba..d9d7891666 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -303,7 +303,7 @@ struct RISCVCPU { > > uint16_t elen; > > bool mmu; > > bool pmp; > > - uint64_t resetvec; > > + target_ulong resetvec; > > } cfg; > > }; > > > > -- > > 2.17.1 > > > >