From: Dylan Jhong <dylan@andestech.com>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>,
<kbastian@mail.uni-paderborn.de>, <sagark@eecs.berkeley.edu>,
<Alistair.Francis@wdc.com>, <palmer@dabbelt.com>
Cc: peter.maydell@linaro.org, alankao@andestech.com,
Dylan Jhong <dylan@andestech.com>,
x5710999x@gmail.com, ruinland@andestech.com, bmeng.cn@gmail.com
Subject: [PATCH V5] target/riscv: Align the data type of reset vector address
Date: Mon, 29 Mar 2021 11:48:01 +0800 [thread overview]
Message-ID: <20210329034801.22667-1-dylan@andestech.com> (raw)
Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b..4ac901245a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature)
env->features |= (1ULL << feature);
}
-static void set_resetvec(CPURISCVState *env, int resetvec)
+static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
env->resetvec = resetvec;
--
2.17.1
next reply other threads:[~2021-03-29 3:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-29 3:48 Dylan Jhong [this message]
2021-03-29 7:15 ` [PATCH V5] target/riscv: Align the data type of reset vector address Bin Meng
2021-03-30 16:30 ` Alistair Francis
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