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Mon, 29 Mar 2021 04:03:12 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a15sm19297187wrr.53.2021.03.29.04.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 04:03:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0136C1FF92; Mon, 29 Mar 2021 12:03:04 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v1 6/6] tests/i386/test-i386: try and correct constrain 16 bit call (WIP) Date: Mon, 29 Mar 2021 12:03:03 +0100 Message-Id: <20210329110303.15235-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210329110303.15235-1-alex.bennee@linaro.org> References: <20210329110303.15235-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Eduardo Habkost Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Newer compilers complain about non-matching constraints: test-i386.c:1393:5: error: asm operand 2 probably doesn’t match constraints [-Werror] 1393 | asm volatile ("lcall %1, %2" | ^~~ It seems the plain "i" immediate constraint is a little too lax here. What we are actually dealing with is a 32 bit offset into a particular segment. I think that is "Ts" (Address operand without segment register). [AJB: however this just seems to push it a bit further down the road: test-i386.c:1393: Error: operand type mismatch for `lcall' Inline ASM constraints are hard :-/] Signed-off-by: Alex Bennée --- tests/tcg/i386/test-i386.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/tcg/i386/test-i386.c b/tests/tcg/i386/test-i386.c index 18d5609665..6d8aeccfb5 100644 --- a/tests/tcg/i386/test-i386.c +++ b/tests/tcg/i386/test-i386.c @@ -1392,15 +1392,15 @@ void test_code16(void) /* call the first function */ asm volatile ("lcall %1, %2" : "=a" (res) - : "i" (MK_SEL(1)), "i" (&code16_func1): "memory", "cc"); + : "i" (MK_SEL(1)), "Ts" (&code16_func1): "memory", "cc"); printf("func1() = 0x%08x\n", res); asm volatile ("lcall %2, %3" : "=a" (res), "=c" (res2) - : "i" (MK_SEL(1)), "i" (&code16_func2): "memory", "cc"); + : "i" (MK_SEL(1)), "Ts" (&code16_func2): "memory", "cc"); printf("func2() = 0x%08x spdec=%d\n", res, res2); asm volatile ("lcall %1, %2" : "=a" (res) - : "i" (MK_SEL(1)), "i" (&code16_func3): "memory", "cc"); + : "i" (MK_SEL(1)), "Ts" (&code16_func3): "memory", "cc"); printf("func3() = 0x%08x\n", res); } #endif -- 2.20.1