From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64
Date: Wed, 31 Mar 2021 10:18:24 +0800 [thread overview]
Message-ID: <20210331021825.537484-1-bmeng.cn@gmail.com> (raw)
hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2585395bf..2bad396f64 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno)
static int hmode32(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_is_32bit(env)) {
- return 0;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
return hmode(env, csrno);
--
2.25.1
next reply other threads:[~2021-03-31 2:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 2:18 Bin Meng [this message]
2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng
2021-03-31 15:51 ` Alistair Francis
2021-06-15 9:07 ` Bin Meng
2021-06-15 10:42 ` Alistair Francis
2021-03-31 15:03 ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis
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