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([161.81.68.216]) by smtp.gmail.com with ESMTPSA id a13sm2886131pgm.43.2021.03.31.09.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 09:08:50 -0700 (PDT) From: Tom Yan To: qemu-devel@nongnu.org, mst@redhat.com Subject: [PATCH 3/3] pcie_root_port: reorder procedures in realize() Date: Thu, 1 Apr 2021 00:08:35 +0800 Message-Id: <20210331160835.160670-3-tom.ty89@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331160835.160670-1-tom.ty89@gmail.com> References: <20210331160835.160670-1-tom.ty89@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=tom.ty89@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, yamahata@valinux.co.jp, Tom Yan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" There are a bunch of pcie_cap_*_init() in the realize method of the pcie root port devices that do not have return value. They can probably be called after the slot is successfully added to an created chassis (i.e. the slot number to use is final). of them makes use of the slot number. Signed-off-by: Tom Yan --- hw/pci-bridge/pcie_root_port.c | 10 +++++----- hw/pci-bridge/xio3130_downstream.c | 9 +++++---- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index f1cfe9d14a..2bd2d02ccb 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -92,11 +92,6 @@ static void rp_realize(PCIDevice *d, Error **errp) goto err_int; } - pcie_cap_arifwd_init(d); - pcie_cap_deverr_init(d); - pcie_cap_slot_init(d, s); - pcie_cap_root_init(d); - pcie_chassis_create(s->chassis); rc = pcie_chassis_add_slot(s); if (rc < 0) { @@ -104,6 +99,11 @@ static void rp_realize(PCIDevice *d, Error **errp) goto err_pcie_cap; } + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s); + pcie_cap_root_init(d); + rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset, PCI_ERR_SIZEOF, errp); if (rc < 0) { diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 04aae72cd6..b7a92693ee 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -92,10 +92,6 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) if (rc < 0) { goto err_msi; } - pcie_cap_flr_init(d); - pcie_cap_deverr_init(d); - pcie_cap_slot_init(d, s); - pcie_cap_arifwd_init(d); pcie_chassis_create(s->chassis); rc = pcie_chassis_add_slot(s); @@ -104,6 +100,11 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_pcie_cap; } + pcie_cap_flr_init(d); + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s); + pcie_cap_arifwd_init(d); + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, errp); if (rc < 0) { -- 2.31.1