From: Shashi Mallela <shashi.mallela@linaro.org>
To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v2 3/8] hw/intc: GICv3 ITS command queue framework
Date: Wed, 31 Mar 2021 22:41:47 -0400 [thread overview]
Message-ID: <20210401024152.203896-4-shashi.mallela@linaro.org> (raw)
In-Reply-To: <20210401024152.203896-1-shashi.mallela@linaro.org>
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/intc/arm_gicv3_its.c | 347 +++++++++++++++++++++++++++++++++++++++
hw/intc/gicv3_internal.h | 41 +++++
2 files changed, 388 insertions(+)
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 81373f049d..fcac33c836 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -28,6 +28,347 @@ struct GICv3ITSClass {
void (*parent_reset)(DeviceState *dev);
};
+static MemTxResult process_sync(GICv3ITSState *s, uint32_t offset)
+{
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ uint64_t rdbase;
+ uint64_t value;
+ bool pta = false;
+ MemTxResult res = MEMTX_OK;
+
+ offset += NUM_BYTES_IN_DW;
+ offset += NUM_BYTES_IN_DW;
+
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ if (FIELD_EX64(s->typer, GITS_TYPER, PTA)) {
+ /*
+ * only bits[47:16] are considered instead of bits [51:16]
+ * since with a physical address the target address must be
+ * 64KB aligned
+ */
+ rdbase = (value >> RDBASE_OFFSET) & RDBASE_MASK;
+ pta = true;
+ } else {
+ rdbase = (value >> RDBASE_OFFSET) & RDBASE_PROCNUM_MASK;
+ }
+
+ if (!pta && (rdbase < (s->gicv3->num_cpu))) {
+ /*
+ * Current implementation makes a blocking synchronous call
+ * for every command issued earlier,hence the internal state
+ * is already consistent by the time SYNC command is executed.
+ */
+ }
+
+ offset += NUM_BYTES_IN_DW;
+ return res;
+}
+
+static void update_cte(GICv3ITSState *s, uint16_t icid, uint64_t cte)
+{
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ uint64_t value;
+ uint8_t page_sz_type;
+ uint64_t l2t_addr;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t page_sz = 0;
+ uint32_t max_l2_entries;
+
+ if (s->ct.indirect) {
+ /* 2 level table */
+ page_sz_type = FIELD_EX64(s->baser[1], GITS_BASER, PAGESIZE);
+
+ if (page_sz_type == 0) {
+ page_sz = GITS_ITT_PAGE_SIZE_0;
+ } else if (page_sz_type == 1) {
+ page_sz = GITS_ITT_PAGE_SIZE_1;
+ } else if (page_sz_type == 2) {
+ page_sz = GITS_ITT_PAGE_SIZE_2;
+ }
+
+ l2t_id = icid / (page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->ct.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, NULL);
+
+ valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
+
+ if (valid_l2t) {
+ max_l2_entries = page_sz / s->ct.entry_sz;
+
+ l2t_addr = (value >> page_sz_type) &
+ ((1ULL << (51 - page_sz_type)) - 1);
+
+ address_space_write(as, l2t_addr +
+ ((icid % max_l2_entries) * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED,
+ &cte, sizeof(cte));
+ }
+ } else {
+ /* Flat level table */
+ address_space_write(as, s->ct.base_addr + (icid * GITS_CTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &cte,
+ sizeof(cte));
+ }
+}
+
+static MemTxResult process_mapc(GICv3ITSState *s, uint32_t offset)
+{
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ uint16_t icid;
+ uint64_t rdbase;
+ bool valid;
+ bool pta = false;
+ MemTxResult res = MEMTX_OK;
+ uint64_t cte_entry;
+ uint64_t value;
+
+ offset += NUM_BYTES_IN_DW;
+ offset += NUM_BYTES_IN_DW;
+
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+
+ icid = value & ICID_MASK;
+
+ if (FIELD_EX64(s->typer, GITS_TYPER, PTA)) {
+ /*
+ * only bits[47:16] are considered instead of bits [51:16]
+ * since with a physical address the target address must be
+ * 64KB aligned
+ */
+ rdbase = (value >> RDBASE_OFFSET) & RDBASE_MASK;
+ pta = true;
+ } else {
+ rdbase = (value >> RDBASE_OFFSET) & RDBASE_PROCNUM_MASK;
+ }
+
+ valid = (value >> VALID_SHIFT) & VALID_MASK;
+
+ if (valid) {
+ if ((icid > s->ct.max_collids) || (!pta &&
+ (rdbase > s->gicv3->num_cpu))) {
+ if (FIELD_EX64(s->typer, GITS_TYPER, SEIS)) {
+ /* Generate System Error here if supported */
+ }
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid collection table attributes "
+ "icid %d rdbase %lu\n", __func__, icid, rdbase);
+ /*
+ * in this implementation,in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ if (s->ct.valid) {
+ /* add mapping entry to collection table */
+ cte_entry = (valid & VALID_MASK) |
+ (pta ? ((rdbase & RDBASE_MASK) << 1ULL) :
+ ((rdbase & RDBASE_PROCNUM_MASK) << 1ULL));
+
+ update_cte(s, icid, cte_entry);
+ }
+ }
+ } else {
+ if (s->ct.valid) {
+ /* remove mapping entry from collection table */
+ cte_entry = 0;
+
+ update_cte(s, icid, cte_entry);
+ }
+ }
+
+ offset += NUM_BYTES_IN_DW;
+ offset += NUM_BYTES_IN_DW;
+
+ return res;
+}
+
+static void update_dte(GICv3ITSState *s, uint32_t devid, uint64_t dte)
+{
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ uint64_t value;
+ uint8_t page_sz_type;
+ uint64_t l2t_addr;
+ bool valid_l2t;
+ uint32_t l2t_id;
+ uint32_t page_sz = 0;
+ uint32_t max_l2_entries;
+
+ if (s->dt.indirect) {
+ /* 2 level table */
+ page_sz_type = FIELD_EX64(s->baser[0], GITS_BASER, PAGESIZE);
+
+ if (page_sz_type == 0) {
+ page_sz = GITS_ITT_PAGE_SIZE_0;
+ } else if (page_sz_type == 1) {
+ page_sz = GITS_ITT_PAGE_SIZE_1;
+ } else if (page_sz_type == 2) {
+ page_sz = GITS_ITT_PAGE_SIZE_2;
+ }
+
+ l2t_id = devid / (page_sz / L1TABLE_ENTRY_SIZE);
+
+ value = address_space_ldq_le(as,
+ s->dt.base_addr +
+ (l2t_id * L1TABLE_ENTRY_SIZE),
+ MEMTXATTRS_UNSPECIFIED, NULL);
+
+ valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
+
+ if (valid_l2t) {
+ max_l2_entries = page_sz / s->dt.entry_sz;
+
+ l2t_addr = (value >> page_sz_type) &
+ ((1ULL << (51 - page_sz_type)) - 1);
+
+ address_space_write(as, l2t_addr +
+ ((devid % max_l2_entries) * GITS_DTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &dte, sizeof(dte));
+ }
+ } else {
+ /* Flat level table */
+ address_space_write(as, s->dt.base_addr + (devid * GITS_DTE_SIZE),
+ MEMTXATTRS_UNSPECIFIED, &dte, sizeof(dte));
+ }
+}
+
+static MemTxResult process_mapd(GICv3ITSState *s, uint64_t value,
+ uint32_t offset)
+{
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ uint32_t devid;
+ uint8_t size;
+ uint64_t itt_addr;
+ bool valid;
+ MemTxResult res = MEMTX_OK;
+ uint64_t dte_entry = 0;
+
+ devid = (value >> DEVID_OFFSET) & DEVID_MASK;
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ size = (value & SIZE_MASK);
+
+ offset += NUM_BYTES_IN_DW;
+ value = address_space_ldq_le(as, s->cq.base_addr + offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ itt_addr = (value >> ITTADDR_OFFSET) & ITTADDR_MASK;
+
+ valid = (value >> VALID_SHIFT) & VALID_MASK;
+
+ if (valid) {
+ if ((devid > s->dt.max_devids) ||
+ (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) {
+ if (FIELD_EX64(s->typer, GITS_TYPER, SEIS)) {
+ /* Generate System Error here if supported */
+ }
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid device table attributes "
+ "devid %d or size %d\n", __func__, devid, size);
+ /*
+ * in this implementation,in case of error
+ * we ignore this command and move onto the next
+ * command in the queue
+ */
+ } else {
+ if (s->dt.valid) {
+ /* add mapping entry to device table */
+ dte_entry = (valid & VALID_MASK) |
+ ((size & SIZE_MASK) << 1U) |
+ ((itt_addr & ITTADDR_MASK) << 6ULL);
+
+ update_dte(s, devid, dte_entry);
+ }
+ }
+ } else {
+ if (s->dt.valid) {
+ /* remove mapping entry from device table */
+ dte_entry = 0;
+ update_dte(s, devid, dte_entry);
+ }
+ }
+
+ offset += NUM_BYTES_IN_DW;
+ offset += NUM_BYTES_IN_DW;
+
+ return res;
+}
+
+/*
+ * Current implementation blocks until all
+ * commands are processed
+ */
+static MemTxResult process_cmdq(GICv3ITSState *s)
+{
+ uint32_t wr_offset = 0;
+ uint32_t rd_offset = 0;
+ uint32_t cq_offset = 0;
+ uint64_t data;
+ AddressSpace *as = &s->gicv3->sysmem_as;
+ MemTxResult res = MEMTX_OK;
+ uint8_t cmd;
+
+ wr_offset = FIELD_EX64(s->cwriter, GITS_CWRITER, OFFSET);
+
+ if (wr_offset > s->cq.max_entries) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid write offset "
+ "%d\n", __func__, wr_offset);
+ res = MEMTX_ERROR;
+ return res;
+ }
+
+ rd_offset = FIELD_EX64(s->creadr, GITS_CREADR, OFFSET);
+
+ while (wr_offset != rd_offset) {
+ cq_offset = (rd_offset * GITS_CMDQ_ENTRY_SIZE);
+ data = address_space_ldq_le(as, s->cq.base_addr + cq_offset,
+ MEMTXATTRS_UNSPECIFIED, &res);
+ cmd = (data & CMD_MASK);
+
+ switch (cmd) {
+ case GITS_CMD_INT:
+ break;
+ case GITS_CMD_CLEAR:
+ break;
+ case GITS_CMD_SYNC:
+ res = process_sync(s, cq_offset);
+ break;
+ case GITS_CMD_MAPD:
+ res = process_mapd(s, data, cq_offset);
+ break;
+ case GITS_CMD_MAPC:
+ res = process_mapc(s, cq_offset);
+ break;
+ case GITS_CMD_MAPTI:
+ break;
+ case GITS_CMD_MAPI:
+ break;
+ case GITS_CMD_DISCARD:
+ break;
+ default:
+ break;
+ }
+ if (res == MEMTX_OK) {
+ rd_offset++;
+ rd_offset %= s->cq.max_entries;
+ s->creadr = FIELD_DP64(s->creadr, GITS_CREADR, OFFSET, rd_offset);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: %x cmd processing failed!!\n", __func__, cmd);
+ break;
+ }
+ }
+ return res;
+}
+
static bool extract_table_params(GICv3ITSState *s, int index)
{
uint16_t num_pages = 0;
@@ -282,6 +623,9 @@ static MemTxResult its_writel(GICv3ITSState *s, hwaddr offset,
break;
case GITS_CWRITER:
s->cwriter = deposit64(s->cwriter, 0, 32, value);
+ if ((s->ctlr & ITS_CTLR_ENABLED) && (s->cwriter != s->creadr)) {
+ result = process_cmdq(s);
+ }
break;
case GITS_CWRITER + 4:
s->cwriter = deposit64(s->cwriter, 32, 32, value);
@@ -416,6 +760,9 @@ static MemTxResult its_writell(GICv3ITSState *s, hwaddr offset,
break;
case GITS_CWRITER:
s->cwriter = value;
+ if ((s->ctlr & ITS_CTLR_ENABLED) && (s->cwriter != s->creadr)) {
+ result = process_cmdq(s);
+ }
break;
case GITS_TYPER:
case GITS_CREADR:
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index b7701e8ca5..7e1ff426ef 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -253,6 +253,12 @@ FIELD(GITS_CBASER, OUTERCACHE, 53, 3)
FIELD(GITS_CBASER, INNERCACHE, 59, 3)
FIELD(GITS_CBASER, VALID, 63, 1)
+FIELD(GITS_CREADR, STALLED, 0, 1)
+FIELD(GITS_CREADR, OFFSET, 5, 15)
+
+FIELD(GITS_CWRITER, RETRY, 0, 1)
+FIELD(GITS_CWRITER, OFFSET, 5, 15)
+
FIELD(GITS_CTLR, ENABLED, 0, 1)
FIELD(GITS_CTLR, QUIESCENT, 31, 1)
@@ -284,6 +290,41 @@ FIELD(GITS_TYPER, CIL, 36, 1)
#define L1TABLE_ENTRY_SIZE 8
#define GITS_CMDQ_ENTRY_SIZE 32
+#define NUM_BYTES_IN_DW 8
+
+#define CMD_MASK 0xff
+
+/* ITS Commands */
+#define GITS_CMD_CLEAR 0x04
+#define GITS_CMD_DISCARD 0x0F
+#define GITS_CMD_INT 0x03
+#define GITS_CMD_MAPC 0x09
+#define GITS_CMD_MAPD 0x08
+#define GITS_CMD_MAPI 0x0B
+#define GITS_CMD_MAPTI 0x0A
+#define GITS_CMD_SYNC 0x05
+
+/* MAPC command fields */
+#define ICID_LEN 16
+#define ICID_MASK ((1U << ICID_LEN) - 1)
+#define RDBASE_LEN 32
+#define RDBASE_OFFSET 16
+#define RDBASE_MASK ((1ULL << RDBASE_LEN) - 1)
+#define RDBASE_PROCNUM_LEN 16
+#define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LEN) - 1)
+
+#define DEVID_OFFSET 32
+#define DEVID_LEN 32
+#define DEVID_MASK ((1ULL << DEVID_LEN) - 1)
+
+/* MAPD command fields */
+#define ITTADDR_LEN 44
+#define ITTADDR_OFFSET 8
+#define ITTADDR_MASK ((1ULL << ITTADDR_LEN) - 1)
+#define SIZE_MASK 0x1f
+
+#define VALID_SHIFT 63
+#define VALID_MASK 0x1
/**
* Default features advertised by this version of ITS
--
2.27.0
next prev parent reply other threads:[~2021-04-01 2:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 2:41 [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-04-01 2:41 ` [PATCH v2 1/8] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-04-16 17:21 ` Peter Maydell
2021-04-29 23:36 ` shashi.mallela
2021-04-30 10:09 ` Peter Maydell
2021-04-30 15:56 ` Shashi Mallela
2021-04-01 2:41 ` [PATCH v2 2/8] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-04-16 18:54 ` Peter Maydell
[not found] ` <937a2923445e3ff629c9799a8579c470d2636375.camel@linaro.org>
2021-04-29 23:37 ` shashi.mallela
2021-04-01 2:41 ` Shashi Mallela [this message]
2021-04-19 10:30 ` [PATCH v2 3/8] hw/intc: GICv3 ITS command queue framework Peter Maydell
2021-04-29 23:38 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 4/8] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-04-19 10:39 ` Peter Maydell
2021-04-01 2:41 ` [PATCH v2 5/8] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-04-19 10:51 ` Peter Maydell
2021-04-29 23:39 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 6/8] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-04-19 12:44 ` Peter Maydell
[not found] ` <89852279ad379f2e50563dd47eb67376262355c0.camel@linaro.org>
2021-04-29 23:40 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela
2021-04-19 12:44 ` Peter Maydell
2021-04-01 2:41 ` [PATCH v2 8/8] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-04-19 12:46 ` Peter Maydell
2021-04-29 23:40 ` shashi.mallela
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