From: Shashi Mallela <shashi.mallela@linaro.org>
To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v2 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC
Date: Wed, 31 Mar 2021 22:41:51 -0400 [thread overview]
Message-ID: <20210401024152.203896-8-shashi.mallela@linaro.org> (raw)
In-Reply-To: <20210401024152.203896-1-shashi.mallela@linaro.org>
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
---
hw/arm/sbsa-ref.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 88dfb2284c..d05cbcae48 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -35,7 +35,7 @@
#include "hw/boards.h"
#include "hw/ide/internal.h"
#include "hw/ide/ahci_internal.h"
-#include "hw/intc/arm_gicv3_common.h"
+#include "hw/intc/arm_gicv3_its_common.h"
#include "hw/loader.h"
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
@@ -65,6 +65,7 @@ enum {
SBSA_CPUPERIPHS,
SBSA_GIC_DIST,
SBSA_GIC_REDIST,
+ SBSA_GIC_ITS,
SBSA_SECURE_EC,
SBSA_GWDT,
SBSA_GWDT_REFRESH,
@@ -108,6 +109,7 @@ static const MemMapEntry sbsa_ref_memmap[] = {
[SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
+ [SBSA_GIC_ITS] = { 0x44090000, 0x00020000 },
[SBSA_SECURE_EC] = { 0x50000000, 0x00001000 },
[SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 },
[SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 },
@@ -378,7 +380,20 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram);
}
-static void create_gic(SBSAMachineState *sms)
+static void create_its(SBSAMachineState *sms)
+{
+ DeviceState *dev;
+
+ dev = qdev_new(TYPE_ARM_GICV3_ITS);
+ SysBusDevice *s = SYS_BUS_DEVICE(dev);
+
+ object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic),
+ &error_abort);
+ sysbus_realize_and_unref(s, &error_fatal);
+ sysbus_mmio_map(s, 0, sbsa_ref_memmap[SBSA_GIC_ITS].base);
+}
+
+static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
{
unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
SysBusDevice *gicbusdev;
@@ -405,6 +420,10 @@ static void create_gic(SBSAMachineState *sms)
qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
+ object_property_set_link(OBJECT(sms->gic), "sysmem", OBJECT(mem),
+ &error_fatal);
+ qdev_prop_set_bit(sms->gic, "has-lpi", true);
+
gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_realize_and_unref(gicbusdev, &error_fatal);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
@@ -451,6 +470,7 @@ static void create_gic(SBSAMachineState *sms)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
+ create_its(sms);
}
static void create_uart(const SBSAMachineState *sms, int uart,
@@ -763,7 +783,7 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem);
- create_gic(sms);
+ create_gic(sms, sysmem);
create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
--
2.27.0
next prev parent reply other threads:[~2021-04-01 2:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 2:41 [PATCH v2 0/8] GICv3 LPI and ITS feature implementation Shashi Mallela
2021-04-01 2:41 ` [PATCH v2 1/8] hw/intc: GICv3 ITS initial framework Shashi Mallela
2021-04-16 17:21 ` Peter Maydell
2021-04-29 23:36 ` shashi.mallela
2021-04-30 10:09 ` Peter Maydell
2021-04-30 15:56 ` Shashi Mallela
2021-04-01 2:41 ` [PATCH v2 2/8] hw/intc: GICv3 ITS register definitions added Shashi Mallela
2021-04-16 18:54 ` Peter Maydell
[not found] ` <937a2923445e3ff629c9799a8579c470d2636375.camel@linaro.org>
2021-04-29 23:37 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 3/8] hw/intc: GICv3 ITS command queue framework Shashi Mallela
2021-04-19 10:30 ` Peter Maydell
2021-04-29 23:38 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 4/8] hw/intc: GICv3 ITS Command processing Shashi Mallela
2021-04-19 10:39 ` Peter Maydell
2021-04-01 2:41 ` [PATCH v2 5/8] hw/intc: GICv3 ITS Feature enablement Shashi Mallela
2021-04-19 10:51 ` Peter Maydell
2021-04-29 23:39 ` shashi.mallela
2021-04-01 2:41 ` [PATCH v2 6/8] hw/intc: GICv3 redistributor ITS processing Shashi Mallela
2021-04-19 12:44 ` Peter Maydell
[not found] ` <89852279ad379f2e50563dd47eb67376262355c0.camel@linaro.org>
2021-04-29 23:40 ` shashi.mallela
2021-04-01 2:41 ` Shashi Mallela [this message]
2021-04-19 12:44 ` [PATCH v2 7/8] hw/arm/sbsa-ref: add ITS support in SBSA GIC Peter Maydell
2021-04-01 2:41 ` [PATCH v2 8/8] hw/arm/virt: add ITS support in virt GIC Shashi Mallela
2021-04-19 12:46 ` Peter Maydell
2021-04-29 23:40 ` shashi.mallela
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