[PATCH 23/27] arcv3: BCR and AUX register changes

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From: cupertinomiranda@gmail.com
To: qemu-devel@nongnu.org
Cc: shahab@synopsys.com, linux-snps-arc@lists.infradead.org,
	claziss@synopsys.com, cmiranda@synopsys.com
Subject: [PATCH 23/27] arcv3: BCR and AUX register changes
Date: Mon,  5 Apr 2021 15:31:34 +0100	[thread overview]
Message-ID: <20210405143138.17016-24-cupertinomiranda@gmail.com> (raw)
In-Reply-To: <20210405143138.17016-1-cupertinomiranda@gmail.com>

From: Cupertino Miranda <cmiranda@synopsys.com>

---
 target/arc/regs-detail.def | 40 ++++++++++++++++++++++++++++++++++++++
 target/arc/regs-impl.c     |  5 +++++
 target/arc/regs.def        | 20 +++++++++++++++++++
 3 files changed, 65 insertions(+)

diff --git a/target/arc/regs-detail.def b/target/arc/regs-detail.def
index 6f0cc94809..48b26d6cb0 100644
--- a/target/arc/regs-detail.def
+++ b/target/arc/regs-detail.def
@@ -39,8 +39,10 @@ DEF(0xa,   ARC_OPCODE_ARCALL,  NONE, status32)
 DEF(0xb,   ARC_OPCODE_ARCV2,   NONE, status32_p0)
 DEF(0xc,   ARC_OPCODE_ARCv2EM, NONE, sec_extra)
 DEF(0xd,   ARC_OPCODE_ARCV2,   NONE, aux_user_sp)
+DEF(0xd,   ARC_OPCODE_V3_ALL,  NONE, aux_user_sp)
 DEF(0xe,   ARC_OPCODE_ARC700,  NONE, clk_enable)
 DEF(0xe,   ARC_OPCODE_ARCV2,   NONE, aux_irq_ctrl)
+DEF(0xe,   ARC_OPCODE_V3_ALL,  NONE, aux_irq_ctrl)
 DEF(0xf,   ARC_OPCODE_ARC700,  NONE, bpu_flush)
 DEF(0xf,   ARC_OPCODE_ARCv2HS, NONE, debugi)
 DEF(0x10,  ARC_OPCODE_ARCV1,   NONE, ivic)
@@ -75,6 +77,7 @@ DEF(0x23,  ARC_OPCODE_ARCALL,  NONE, limit0)
 DEF(0x24,  ARC_OPCODE_ARCV1,   NONE, pcport)
 DEF(0x25,  ARC_OPCODE_ARC700,  NONE, int_vector_base)
 DEF(0x25,  ARC_OPCODE_ARCV2,   NONE, int_vector_base)
+DEF(0x25,  ARC_OPCODE_V3_ALL,  NONE, int_vector_base)
 DEF(0x26,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_mode)
 DEF(0x27,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm0)
 DEF(0x28,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm1)
@@ -116,6 +119,7 @@ DEF(0x41,  ARC_OPCODE_ARCV1,   NONE, aux_macmode)
 DEF(0x42,  ARC_OPCODE_ARC600,  NONE, lsp_newval)
 DEF(0x43,  ARC_OPCODE_ARCV1,   NONE, aux_irq_lv12)
 DEF(0x43,  ARC_OPCODE_ARCV2,   NONE, aux_irq_act)
+DEF(0x43,  ARC_OPCODE_V3_ALL,  NONE, aux_irq_act)
 DEF(0x44,  ARC_OPCODE_ARCV1,   NONE, aux_xmac0)
 DEF(0x45,  ARC_OPCODE_ARCV1,   NONE, aux_xmac1)
 DEF(0x46,  ARC_OPCODE_ARCV1,   NONE, aux_xmac2)
@@ -126,7 +130,9 @@ DEF(0x4a,  ARC_OPCODE_ARCALL,  NONE, dc_ivdl)
 DEF(0x4b,  ARC_OPCODE_ARCALL,  NONE, dc_flsh)
 DEF(0x4c,  ARC_OPCODE_ARCALL,  NONE, dc_fldl)
 DEF(0x4d,  ARC_OPCODE_ARCV2,   NONE, dc_startr)
+DEF(0x4d,  ARC_OPCODE_V3_ALL,  NONE, dc_startr)
 DEF(0x4e,  ARC_OPCODE_ARCV2,   NONE, dc_endr)
+DEF(0x4e,  ARC_OPCODE_V3_ALL,  NONE, dc_endr)
 DEF(0x50,  ARC_OPCODE_NONE,    NONE, hexdata)
 DEF(0x51,  ARC_OPCODE_NONE,    NONE, hexctrl)
 DEF(0x52,  ARC_OPCODE_NONE,    NONE, led)
@@ -191,13 +197,17 @@ DEF(0x100, ARC_OPCODE_ARCALL,  NONE, count1)
 DEF(0x101, ARC_OPCODE_ARCALL,  NONE, control1)
 DEF(0x102, ARC_OPCODE_ARCALL,  NONE, limit1)
 DEF(0x103, ARC_OPCODE_ARCV2,   NONE, aux_rtc_ctrl)
+DEF(0x103, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_ctrl)
 DEF(0x104, ARC_OPCODE_ARCV2,   NONE, aux_rtc_low)
+DEF(0x104, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_low)
 DEF(0x105, ARC_OPCODE_ARCV2,   NONE, aux_rtc_high)
+DEF(0x105, ARC_OPCODE_V3_ALL,  NONE, aux_rtc_high)
 DEF(0x200, ARC_OPCODE_ARCV1,   NONE, aux_irq_lev)
 DEF(0x200, ARC_OPCODE_ARCV2,   NONE, irq_priority_pending)
 DEF(0x201, ARC_OPCODE_ARCALL,  NONE, aux_irq_hint)
 DEF(0x202, ARC_OPCODE_ARC600,  NONE, aux_inter_core_interrupt)
 DEF(0x206, ARC_OPCODE_ARCV2,   NONE, irq_priority)
+DEF(0x206, ARC_OPCODE_V3_ALL,  NONE, irq_priority)
 DEF(0x210, ARC_OPCODE_ARC700,  NONE, aes_aux_0)
 DEF(0x211, ARC_OPCODE_ARC700,  NONE, aes_aux_1)
 DEF(0x212, ARC_OPCODE_ARC700,  NONE, aes_aux_2)
@@ -273,10 +283,15 @@ DEF(0x408, ARC_OPCODE_ARC700,  NONE, tlbcommand)
 DEF(0x409, ARC_OPCODE_ARC700,  NONE, pid)
 DEF(0x409, ARC_OPCODE_ARCALL,  NONE, mpuen)
 DEF(0x40a, ARC_OPCODE_ARCV2,   NONE, icause)
+DEF(0x40a, ARC_OPCODE_V3_ALL,  NONE, icause)
 DEF(0x40b, ARC_OPCODE_ARCV2,   NONE, irq_select)
+DEF(0x40b, ARC_OPCODE_V3_ALL,  NONE, irq_select)
 DEF(0x40c, ARC_OPCODE_ARCV2,   NONE, irq_enable)
+DEF(0x40c, ARC_OPCODE_V3_ALL,  NONE, irq_enable)
 DEF(0x40d, ARC_OPCODE_ARCV2,   NONE, irq_trigger)
+DEF(0x40d, ARC_OPCODE_V3_ALL,  NONE, irq_trigger)
 DEF(0x40f, ARC_OPCODE_ARCV2,   NONE, irq_status)
+DEF(0x40f, ARC_OPCODE_V3_ALL,  NONE, irq_status)
 DEF(0x410, ARC_OPCODE_ARCALL,  NONE, xpu)
 DEF(0x412, ARC_OPCODE_ARCALL,  NONE, bta)
 DEF(0x413, ARC_OPCODE_ARC700,  NONE, bta_l1)
@@ -497,12 +512,17 @@ DEF(0xff, ARC_OPCODE_DEFAULT,  NONE, unimp_bcr)
 /* Actual BCR implementations */
 
 DEF(0x6d, ARC_OPCODE_ARCv2HS, NONE, mpu_build)
+DEF(0x6d, ARC_OPCODE_V3_ALL,  NONE, mpu_build)
 DEF(0x6f, ARC_OPCODE_ARCv2HS, NONE, mmu_build)
 DEF(0x75, ARC_OPCODE_ARCALL, NONE, timer_build)
 DEF(0xf3, ARC_OPCODE_ARCV2,  NONE, irq_build)
+DEF(0xf3, ARC_OPCODE_V3_ALL, NONE, irq_build)
 DEF(0x72, ARC_OPCODE_ARCV2,  NONE, d_cache_build)
+DEF(0x72, ARC_OPCODE_V3_ALL, NONE, d_cache_build)
 DEF(0x77, ARC_OPCODE_ARCV2,  NONE, i_cache_build)
+DEF(0x77, ARC_OPCODE_V3_ALL, NONE, i_cache_build)
 DEF(0x7b, ARC_OPCODE_ARCV2,  NONE, mpy_build)
+DEF(0x7b, ARC_OPCODE_V3_ALL, NONE, mpy_build)
 
 /* OLD BCR definitions */
 /*
@@ -538,3 +558,23 @@ DEF (0xfc,  ARC_OPCODE_ARCALL,  NONE, vlc_build)
 DEF (0xfd,  ARC_OPCODE_ARCALL,  NONE, simd_dma_build)
 DEF (0xfe,  ARC_OPCODE_ARCALL,  NONE, ifetch_queue_build)
 */
+
+/* ARCV3 definitions. */
+
+DEF (0x7,   ARC_OPCODE_V3_ALL,   NONE, memseg)
+DEF (0x16,  ARC_OPCODE_V3_ALL,   NONE, ic_ivir)
+DEF (0x17,  ARC_OPCODE_V3_ALL,   NONE, ic_endr)
+DEF (0x460, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp0)
+DEF (0x461, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp0hi)
+DEF (0x462, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp1)
+DEF (0x463, ARC_OPCODE_V3_ALL,   NONE, mmu_rtp1hi)
+DEF (0x464, ARC_OPCODE_V3_ALL,   NONE, tlbindex)
+DEF (0x465, ARC_OPCODE_V3_ALL,   NONE, mmuv6_tlbcommand)
+DEF (0x466, ARC_OPCODE_V3_ALL,   NONE, mmu_tlb_data0)
+DEF (0x467, ARC_OPCODE_V3_ALL,   NONE, mmu_tlb_data1)
+DEF (0x468, ARC_OPCODE_V3_ALL,   NONE, mmu_ctrl)
+DEF (0x469, ARC_OPCODE_V3_ALL,   NONE, mmu_ttbcr)
+DEF (0x46a, ARC_OPCODE_V3_ALL,   NONE, mmu_mem_attr)
+DEF (0x46b, ARC_OPCODE_V3_ALL,   NONE, mmu_fault_status)
+DEF (0xc1,  ARC_OPCODE_V3_ALL,   NONE, isa_config)
+DEF (0x6f,  ARC_OPCODE_V3_ALL,   NONE, mmuv6_build)
diff --git a/target/arc/regs-impl.c b/target/arc/regs-impl.c
index 18a307fdc4..d7ae57e8cf 100644
--- a/target/arc/regs-impl.c
+++ b/target/arc/regs-impl.c
@@ -46,6 +46,11 @@ static target_ulong get_identity(CPUARCState *env)
         arcver = 0x54;
         break;
 
+    /* TODO: Add V3/ARC32. */
+    case ARC_OPCODE_V3_ARC64:
+        arcver = 0x70;
+        break;
+
     default:
         arcver = 0;
 
diff --git a/target/arc/regs.def b/target/arc/regs.def
index 5dc3764266..9c0e81d884 100644
--- a/target/arc/regs.def
+++ b/target/arc/regs.def
@@ -410,3 +410,23 @@ AUX_REG (xylsbasey, NULL, NULL)
 AUX_REG (aux_rtc_ctrl, aux_timer_get, aux_timer_set)
 AUX_REG (aux_rtc_low, aux_timer_get, aux_timer_set)
 AUX_REG (aux_rtc_high, aux_timer_get, aux_timer_set)
+
+/* ARCV3 specific registers. */
+
+AUX_REG_GETTER(arc_mmuv6_aux_get)
+AUX_REG_SETTER(arc_mmuv6_aux_set)
+
+AUX_REG (mmuv6_build, arc_mmuv6_aux_get, NULL)
+AUX_REG (mmuv6_tlbcommand,  arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+
+AUX_REG (mmu_ctrl, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_rtp0, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_rtp0hi, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_rtp1, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_rtp1hi, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_ttbcr, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_tlb_data0, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_tlb_data1, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_fault_status, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
+AUX_REG (mmu_mem_attr, arc_mmuv6_aux_get, arc_mmuv6_aux_set)
-- 
2.20.1

next prev parent reply	other threads:[~2021-04-05 15:02 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-05 14:31 *** ARC port for review *** cupertinomiranda
2021-04-05 14:31 ` [PATCH 01/27] arc: Add initial core cpu files cupertinomiranda
2021-04-07  0:47   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 02/27] arc: Decoder code cupertinomiranda
2021-04-07  1:25   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 03/27] arc: Opcode definitions table cupertinomiranda
2021-04-05 14:31 ` [PATCH 04/27] arc: TCG and decoder glue code and helpers cupertinomiranda
2021-04-07  2:37   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 05/27] arc: TCG instruction generator and hand-definitions cupertinomiranda
2021-04-07  3:52   ` Richard Henderson
2021-04-07 16:47   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 06/27] arc: semfunc.c tcg code generator cupertinomiranda
2021-04-07 17:14   ` Richard Henderson
2021-04-07 18:33     ` Peter Maydell
2021-04-05 14:31 ` [PATCH 07/27] arc: TCG instruction definitions cupertinomiranda
2021-04-07 19:38   ` Richard Henderson
2021-04-08  0:20   ` Richard Henderson
2021-04-12 14:27     ` Cupertino Miranda
2021-04-05 14:31 ` [PATCH 08/27] arc: Add BCR and AUX registers implementation cupertinomiranda
2021-04-05 14:31 ` [PATCH 09/27] arc: Add IRQ and timer subsystem support cupertinomiranda
2021-04-05 14:31 ` [PATCH 10/27] arc: Add memory management unit (MMU) support cupertinomiranda
2021-04-05 14:31 ` [PATCH 11/27] arc: Add memory protection unit (MPU) support cupertinomiranda
2021-04-05 14:31 ` [PATCH 12/27] arc: Add gdbstub and XML for debugging support cupertinomiranda
2021-04-05 14:31 ` [PATCH 13/27] arc: Add Synopsys ARC emulation boards cupertinomiranda
2021-04-05 14:31 ` [PATCH 14/27] arc: Add support for ARCv2 cupertinomiranda
2021-04-07 20:30   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 15/27] tests/tcg: ARC: Add TCG instruction definition tests cupertinomiranda
2021-04-07 20:38   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 16/27] tests/acceptance: ARC: Add linux boot testing cupertinomiranda
2021-04-07 20:40   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 17/27] arcv3: Core cpu file changes cupertinomiranda
2021-04-05 14:31 ` [PATCH 18/27] arcv3: Decoder code cupertinomiranda
2021-04-07 23:07   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 19/27] arcv3: Opcode definition table cupertinomiranda
2021-04-05 14:31 ` [PATCH 20/27] arcv3: TCG, decoder glue code and helper changes cupertinomiranda
2021-04-07 23:36   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 21/27] arcv3: TCG instruction generator changes cupertinomiranda
2021-04-07 23:43   ` Richard Henderson
2021-04-05 14:31 ` [PATCH 22/27] arcv3: TCG instruction definitions cupertinomiranda
2021-04-07 23:48   ` Richard Henderson
2021-04-05 14:31 ` cupertinomiranda [this message]
2021-04-05 14:31 ` [PATCH 24/27] arcv3: IRQ changes and new MMUv6 WIP cupertinomiranda
2021-04-05 14:31 ` [PATCH 25/27] arcv3: gdbstub changes and new XML files cupertinomiranda
2021-04-05 14:31 ` [PATCH 26/27] arcv3: board changes cupertinomiranda
2021-04-05 14:31 ` [PATCH 27/27] arcv3: Add support for ARCv3 cupertinomiranda
2021-04-06 23:47 ` *** ARC port for review *** Richard Henderson
2021-04-12 14:25   ` Cupertino Miranda

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:6f0cc9480 dfblob:48b26d6cb dfblob:18a307fdc dfblob:d7ae57e8c
dfblob:5dc376426 dfblob:9c0e81d88 )
 OR (
bs:"[PATCH 23/27] arcv3: BCR and AUX register changes" )
	(help)

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