Re: [PATCH] i386/cpu: Expose AVX_VNNI instruction to guset

[Yang Zhong <yang.zhong@intel.com>]

On Tue, Apr 06, 2021 at 09:15:44AM +0200, Philippe Mathieu-Daudé wrote:
> Typo "guest" in subject.
> 
  Philippe, thanks for your comments! It's my fault, let me change it and 
  if there is no any other issue , i will send new version tomorrow. thanks!

  Yang

> On 4/6/21 3:57 AM, Yang Zhong wrote:
> > Expose AVX (VEX-encoded) versions of the Vector Neural Network
> > Instructions to guest.>
> > The bit definition:
> > CPUID.(EAX=7,ECX=1):EAX[bit 4] AVX_VNNI
> > 
> > The following instructions are available when this feature is
> > present in the guest.
> >   1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
> >   2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
> >   3. VPDPWSSD: Multiply and Add Signed Word Integers
> >   4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
> > 
> > As for the kvm related code, please reference Linux commit id 1085a6b585d7.
> > 
> > The release document ref below link:
> > https://software.intel.com/content/www/us/en/develop/download/\
> > intel-architecture-instruction-set-extensions-programming-reference.html
> > 
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> >  target/i386/cpu.c | 4 ++--
> >  target/i386/cpu.h | 2 ++
> >  2 files changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 6b3e9467f1..f0c48f06a2 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -996,7 +996,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> >          .type = CPUID_FEATURE_WORD,
> >          .feat_names = {
> >              NULL, NULL, NULL, NULL,
> > -            NULL, "avx512-bf16", NULL, NULL,
> > +            "avx-vnni", "avx512-bf16", NULL, NULL,
> >              NULL, NULL, NULL, NULL,
> >              NULL, NULL, NULL, NULL,
> >              NULL, NULL, NULL, NULL,
> > @@ -3273,7 +3273,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> >              MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
> >              MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
> >          .features[FEAT_7_1_EAX] =
> > -            CPUID_7_1_EAX_AVX512_BF16,
> > +            CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
> >          /*
> >           * Missing: XSAVES (not supported by some Linux versions,
> >           * including v4.1 to v4.12).
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 570f916878..edc8984448 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -804,6 +804,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
> >  /* Speculative Store Bypass Disable */
> >  #define CPUID_7_0_EDX_SPEC_CTRL_SSBD    (1U << 31)
> >  
> > +/* AVX VNNI Instruction */
> > +#define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
> >  /* AVX512 BFloat16 Instruction */
> >  #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
> >  
> >