From: Ilya Leoshkevich <iii@linux.ibm.com>
To: Cornelia Huck <cohuck@redhat.com>, Thomas Huth <thuth@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
David Hildenbrand <david@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Christian Borntraeger <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org, Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PATCH v3 2/3] target/arm: Make sure that commpage's tb->size != 0
Date: Wed, 14 Apr 2021 15:41:11 +0200 [thread overview]
Message-ID: <20210414134112.25620-3-iii@linux.ibm.com> (raw)
In-Reply-To: <20210414134112.25620-1-iii@linux.ibm.com>
tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.
Fix by pretending that commpage translation blocks have at least one
instruction.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 62b1c2081b..885f69b044 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9060,6 +9060,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
unsigned int insn;
if (arm_pre_translate_insn(dc)) {
+ dc->base.pc_next += 4;
return;
}
--
2.29.2
next prev parent reply other threads:[~2021-04-14 13:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 13:41 [PATCH v3 0/3] accel/tcg: Make sure that tb->size != 0 after translation Ilya Leoshkevich
2021-04-14 13:41 ` [PATCH v3 1/3] target/s390x: Fix translation exception on illegal instruction Ilya Leoshkevich
2021-04-14 14:47 ` David Hildenbrand
2021-04-14 13:41 ` Ilya Leoshkevich [this message]
2021-04-14 13:41 ` [PATCH v3 3/3] accel/tcg: Assert that tb->size != 0 after translation Ilya Leoshkevich
2021-04-14 14:48 ` David Hildenbrand
2021-04-14 16:45 ` Ilya Leoshkevich
2021-04-14 18:03 ` Max Filippov
2021-04-14 19:43 ` Richard Henderson
2021-04-15 1:23 ` Max Filippov
2021-04-15 11:14 ` Ilya Leoshkevich
2021-04-15 14:33 ` Richard Henderson
2021-04-15 15:02 ` Peter Maydell
2021-04-15 20:20 ` Max Filippov
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