From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v4 for-6.1 00/39] target/arm: enforce alignment
Date: Fri, 16 Apr 2021 11:59:29 -0700 [thread overview]
Message-ID: <20210416185959.1520974-1-richard.henderson@linaro.org> (raw)
Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org
("[PATCH v5 for-6.1 0/9] target/arm mte fixes")
Patches lacking review:
02-target-arm-Rename-TBFLAG_A32-SCTLR_B.patch
03-target-arm-Rename-TBFLAG_ANY-PSTATE_SS.patch
04-target-arm-Add-wrapper-macros-for-accessing-tbfla.patch
05-target-arm-Introduce-CPUARMTBFlags.patch
06-target-arm-Move-mode-specific-TB-flags-to-tb-cs_b.patch
07-target-arm-Move-TBFLAG_AM32-bits-to-the-top.patch
08-target-arm-Move-TBFLAG_ANY-bits-to-the-bottom.patch
09-target-arm-Add-ALIGN_MEM-to-TBFLAG_ANY.patch
21-target-arm-Enforce-alignment-for-VLDn-all-lanes.patch
Changes for v4:
* Rebase on mte fixes and fixup minor conflict.
Changes for v3:
* Move TBFLAG_{A64,A32,M32,AM32} to tb->cs_base, leaving only
TBFLAG_ANY in tb->flags. This solves our current problem of
running out of bits in tb->flags.
* Dropped "Enforce alignment for sve unpredicated LDR/STR";
there are more changes required for SVE.
Changes for v2:
* Rearranged things a bit, which has made it easy to support
SCTLR.A/CCR.UNALIGN_TRAP. At least for non-sve code, where
we issue tcg load/store operations. Predicated sve load/stores
will require more work within the helpers.
r~
Richard Henderson (30):
target/arm: Fix decode of align in VLDST_single
target/arm: Rename TBFLAG_A32, SCTLR_B
target/arm: Rename TBFLAG_ANY, PSTATE_SS
target/arm: Add wrapper macros for accessing tbflags
target/arm: Introduce CPUARMTBFlags
target/arm: Move mode specific TB flags to tb->cs_base
target/arm: Move TBFLAG_AM32 bits to the top
target/arm: Move TBFLAG_ANY bits to the bottom
target/arm: Add ALIGN_MEM to TBFLAG_ANY
target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness
target/arm: Enforce word alignment for LDRD/STRD
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
target/arm: Enforce alignment for LDM/STM
target/arm: Enforce alignment for RFE
target/arm: Enforce alignment for SRS
target/arm: Enforce alignment for VLDM/VSTM
target/arm: Enforce alignment for VLDR/VSTR
target/arm: Enforce alignment for VLDn (all lanes)
target/arm: Enforce alignment for VLDn/VSTn (multiple)
target/arm: Enforce alignment for VLDn/VSTn (single)
target/arm: Use finalize_memop for aa64 gpr load/store
target/arm: Use finalize_memop for aa64 fpr load/store
target/arm: Enforce alignment for aa64 load-acq/store-rel
target/arm: Use MemOp for size + endian in aa64 vector ld/st
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
target/arm: Enforce alignment for sve LD1R
target/arm/cpu.h | 105 ++++++++-----
target/arm/translate.h | 38 +++++
target/arm/neon-ls.decode | 4 +-
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 160 +++++++++++---------
target/arm/translate-a64.c | 214 +++++++++++++-------------
target/arm/translate-sve.c | 2 +-
target/arm/translate.c | 258 +++++++++++++++++---------------
target/arm/translate-neon.c.inc | 117 ++++++++++++---
target/arm/translate-vfp.c.inc | 20 +--
10 files changed, 555 insertions(+), 365 deletions(-)
--
2.25.1
next reply other threads:[~2021-04-16 19:03 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-16 18:59 Richard Henderson [this message]
2021-04-16 18:59 ` [PATCH v4 01/30] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-16 18:59 ` [PATCH v4 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-04-19 17:03 ` Peter Maydell
2021-04-19 18:19 ` Richard Henderson
2021-04-16 18:59 ` [PATCH v4 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 04/30] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 05/30] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-04-19 17:06 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 06/30] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-04-19 17:08 ` Peter Maydell
2021-04-19 18:24 ` Richard Henderson
2021-04-16 18:59 ` [PATCH v4 07/30] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-04-19 17:07 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 08/30] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-04-19 17:04 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-04-19 17:07 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-04-16 18:59 ` [PATCH v4 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-04-16 18:59 ` [PATCH v4 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-04-16 18:59 ` [PATCH v4 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-04-16 18:59 ` [PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-04-16 18:59 ` [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-04-16 18:59 ` [PATCH v4 16/30] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-04-16 18:59 ` [PATCH v4 17/30] target/arm: Enforce alignment for RFE Richard Henderson
2021-04-16 18:59 ` [PATCH v4 18/30] target/arm: Enforce alignment for SRS Richard Henderson
2021-04-16 18:59 ` [PATCH v4 19/30] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-04-16 18:59 ` [PATCH v4 20/30] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-04-16 18:59 ` [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-04-19 17:09 ` Peter Maydell
2021-04-16 18:59 ` [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-04-16 18:59 ` [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-04-16 18:59 ` [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-04-16 18:59 ` [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-04-16 18:59 ` [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-04-16 18:59 ` [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-16 19:17 ` [PATCH v4 for-6.1 00/39] target/arm: enforce alignment Peter Maydell
2021-04-16 19:23 ` Richard Henderson
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