From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org,
lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br,
matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au
Subject: [PATCH v3 06/30] target/ppc: Split out decode_legacy
Date: Thu, 29 Apr 2021 18:15:19 -0700 [thread overview]
Message-ID: <20210430011543.1017113-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 115 +++++++++++++++++++++++------------------
1 file changed, 64 insertions(+), 51 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ee25badba2..ebe5afe7ae 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7876,6 +7876,62 @@ void ppc_cpu_dump_statistics(CPUState *cs, int flags)
#endif
}
+static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn)
+{
+ opc_handler_t **table, *handler;
+ uint32_t inval;
+
+ ctx->opcode = insn;
+
+ LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
+ insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ ctx->le_mode ? "little" : "big");
+
+ table = cpu->opcodes;
+ handler = table[opc1(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc2(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc3(insn)];
+ if (is_indirect_opcode(handler)) {
+ table = ind_table(handler);
+ handler = table[opc4(insn)];
+ }
+ }
+ }
+
+ /* Is opcode *REALLY* valid ? */
+ if (unlikely(handler->handler == &gen_invalid)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
+ "%02x - %02x - %02x - %02x (%08x) "
+ TARGET_FMT_lx "\n",
+ opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ insn, ctx->cia);
+ return false;
+ }
+
+ if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
+ && Rc(insn))) {
+ inval = handler->inval2;
+ } else {
+ inval = handler->inval1;
+ }
+
+ if (unlikely((insn & inval) != 0)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
+ "%02x - %02x - %02x - %02x (%08x) "
+ TARGET_FMT_lx "\n", insn & inval,
+ opc1(insn), opc2(insn), opc3(insn), opc4(insn),
+ insn, ctx->cia);
+ return false;
+ }
+
+ handler->handler(ctx);
+ return true;
+}
+
static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
@@ -7997,66 +8053,23 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = cs->env_ptr;
- opc_handler_t **table, *handler;
+ uint32_t insn;
+ bool ok;
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
ctx->cia = ctx->base.pc_next;
- ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
- need_byteswap(ctx));
-
- LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
- ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->le_mode ? "little" : "big");
+ insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx));
ctx->base.pc_next += 4;
- table = cpu->opcodes;
- handler = table[opc1(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc2(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc3(ctx->opcode)];
- if (is_indirect_opcode(handler)) {
- table = ind_table(handler);
- handler = table[opc4(ctx->opcode)];
- }
- }
- }
- /* Is opcode *REALLY* valid ? */
- if (unlikely(handler->handler == &gen_invalid)) {
- qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
- "%02x - %02x - %02x - %02x (%08x) "
- TARGET_FMT_lx " %d\n",
- opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->cia, (int)msr_ir);
- } else {
- uint32_t inval;
- if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
- && Rc(ctx->opcode))) {
- inval = handler->inval2;
- } else {
- inval = handler->inval1;
- }
-
- if (unlikely((ctx->opcode & inval) != 0)) {
- qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
- "%02x - %02x - %02x - %02x (%08x) "
- TARGET_FMT_lx "\n", ctx->opcode & inval,
- opc1(ctx->opcode), opc2(ctx->opcode),
- opc3(ctx->opcode), opc4(ctx->opcode),
- ctx->opcode, ctx->cia);
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
- ctx->base.is_jmp = DISAS_NORETURN;
- return;
- }
+ ok = decode_legacy(cpu, ctx, insn);
+ if (!ok) {
+ gen_invalid(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
- (*(handler->handler))(ctx);
+
#if defined(DO_PPC_STATISTICS)
handler->count++;
#endif
--
2.25.1
next prev parent reply other threads:[~2021-04-30 1:27 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 1:15 [PATCH v3 00/30] Base for adding PowerPC 64-bit instructions Richard Henderson
2021-04-30 1:15 ` [PATCH v3 01/30] decodetree: Introduce whex and whexC helpers Richard Henderson
2021-04-30 13:01 ` Luis Fernando Fujita Pires
2021-05-03 22:32 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 02/30] decodetree: More use of f-strings Richard Henderson
2021-04-30 13:01 ` Luis Fernando Fujita Pires
2021-05-03 22:33 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 03/30] decodetree: Add support for 64-bit instructions Richard Henderson
2021-04-30 13:03 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 04/30] decodetree: Extend argument set syntax to allow types Richard Henderson
2021-04-30 13:29 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 05/30] target/ppc: Add cia field to DisasContext Richard Henderson
2021-04-30 20:08 ` Bruno Piazera Larsen
2021-04-30 20:35 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` Richard Henderson [this message]
2021-04-30 20:36 ` [PATCH v3 06/30] target/ppc: Split out decode_legacy Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 07/30] target/ppc: Move DISAS_NORETURN setting into gen_exception* Richard Henderson
2021-05-03 12:58 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 08/30] target/ppc: Remove special case for POWERPC_SYSCALL Richard Henderson
2021-05-03 12:59 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 09/30] target/ppc: Remove special case for POWERPC_EXCP_TRAP Richard Henderson
2021-05-03 13:00 ` Luis Fernando Fujita Pires
2021-04-30 1:15 ` [PATCH v3 10/30] target/ppc: Simplify gen_debug_exception Richard Henderson
2021-04-30 1:15 ` [PATCH v3 11/30] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} Richard Henderson
2021-04-30 1:15 ` [PATCH v3 12/30] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT Richard Henderson
2021-04-30 1:15 ` [PATCH v3 13/30] target/ppc: Remove unnecessary gen_io_end calls Richard Henderson
2021-04-30 1:15 ` [PATCH v3 14/30] target/ppc: Introduce gen_icount_io_start Richard Henderson
2021-04-30 1:15 ` [PATCH v3 15/30] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE Richard Henderson
2021-04-30 1:15 ` [PATCH v3 16/30] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN Richard Henderson
2021-04-30 1:15 ` [PATCH v3 17/30] target/ppc: Remove DisasContext.exception Richard Henderson
2021-04-30 13:00 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 18/30] target/ppc: Move single-step check to ppc_tr_tb_stop Richard Henderson
2021-04-30 1:15 ` [PATCH v3 19/30] target/ppc: Tidy exception vs exit_tb Richard Henderson
2021-04-30 1:15 ` [PATCH v3 20/30] target/ppc: Mark helper_raise_exception* as noreturn Richard Henderson
2021-05-03 22:36 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 21/30] target/ppc: Use translator_loop_temp_check Richard Henderson
2021-04-30 1:15 ` [PATCH v3 22/30] target/ppc: Introduce macros to check isa extensions Richard Henderson
2021-05-03 22:37 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 23/30] target/ppc: Add infrastructure for prefixed insns Richard Henderson
2021-04-30 1:15 ` [PATCH v3 24/30] target/ppc: Move page crossing check to ppc_tr_translate_insn Richard Henderson
2021-04-30 1:26 ` Richard Henderson
2021-04-30 1:15 ` [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Richard Henderson
2021-04-30 11:23 ` Luis Fernando Fujita Pires
2021-04-30 14:23 ` Richard Henderson
2021-04-30 18:45 ` Luis Fernando Fujita Pires
2021-04-30 19:11 ` Richard Henderson
2021-04-30 20:32 ` Luis Fernando Fujita Pires
2021-04-30 22:29 ` Richard Henderson
2021-04-30 14:05 ` Matheus K. Ferst
2021-04-30 14:31 ` Richard Henderson
2021-04-30 18:02 ` Matheus K. Ferst
2021-04-30 18:43 ` Richard Henderson
2021-04-30 23:29 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 26/30] target/ppc: Implement PNOP Richard Henderson
2021-05-03 22:41 ` Philippe Mathieu-Daudé
2021-04-30 1:15 ` [PATCH v3 27/30] target/ppc: Move D/DS/X-form integer loads to decodetree Richard Henderson
2021-04-30 23:54 ` Matheus K. Ferst
2021-05-01 0:50 ` Richard Henderson
2021-05-03 12:28 ` Matheus K. Ferst
2021-04-30 1:15 ` [PATCH v3 28/30] target/ppc: Implement prefixed integer load instructions Richard Henderson
2021-04-30 1:15 ` [PATCH v3 29/30] target/ppc: Move D/DS/X-form integer stores to decodetree Richard Henderson
2021-04-30 1:15 ` [PATCH v3 30/30] target/ppc: Implement prefixed integer store instructions Richard Henderson
2021-04-30 1:48 ` [PATCH v3 00/30] Base for adding PowerPC 64-bit instructions no-reply
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