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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v2 4/8] hw/riscv: Support the official PLIC DT bindings
Date: Fri, 30 Apr 2021 15:12:58 +0800	[thread overview]
Message-ID: <20210430071302.1489082-4-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20210430071302.1489082-1-bmeng.cn@gmail.com>

From: Bin Meng <bin.meng@windriver.com>

The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

Changes in v2:
- use "static const char * const" for plic_compat

 hw/riscv/sifive_u.c | 6 +++++-
 hw/riscv/virt.c     | 6 +++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fd5cf7513b..b55e56890c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -102,6 +102,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
     };
+    static const char * const plic_compat[2] = {
+        "sifive,plic-1.0.0", "riscv,plic0"
+    };
 
     if (ms->dtb) {
         fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
@@ -271,7 +274,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
         (long)memmap[SIFIVE_U_DEV_PLIC].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
+    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
+        (char **)&plic_compat, ARRAY_SIZE(plic_compat));
     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4b32dc734f..8a8ff04dab 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -198,6 +198,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
     };
+    static const char * const plic_compat[2] = {
+        "sifive,plic-1.0.0", "riscv,plic0"
+    };
 
     if (mc->dtb) {
         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -320,7 +323,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
             "#address-cells", FDT_PLIC_ADDR_CELLS);
         qemu_fdt_setprop_cell(fdt, plic_name,
             "#interrupt-cells", FDT_PLIC_INT_CELLS);
-        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+        qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
+            (char **)&plic_compat, ARRAY_SIZE(plic_compat));
         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-- 
2.25.1



  parent reply	other threads:[~2021-04-30  7:17 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30  7:12 [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Bin Meng
2021-04-30  7:12 ` [PATCH v2 2/8] hw/riscv: virt: " Bin Meng
2021-04-30  7:12 ` [PATCH v2 3/8] hw/riscv: Support the official CLINT DT bindings Bin Meng
2021-04-30  7:12 ` Bin Meng [this message]
2021-04-30  7:12 ` [PATCH v2 5/8] docs/system/riscv: Correct the indentation level of supported devices Bin Meng
2021-05-03  3:00   ` Alistair Francis
2021-04-30  7:13 ` [PATCH v2 6/8] docs/system/riscv: sifive_u: Document '-dtb' usage Bin Meng
2021-04-30  7:13 ` [PATCH v2 7/8] hw/riscv: Use macros for BIOS image names Bin Meng
2021-04-30  7:13 ` [PATCH v2 8/8] hw/riscv: microchip_pfsoc: Support direct kernel boot Bin Meng
2021-05-31  2:33 ` [PATCH v2 1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Bin Meng
2021-06-01  6:41   ` Alistair Francis

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