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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1
Date: Fri, 30 Apr 2021 11:33:59 +0100	[thread overview]
Message-ID: <20210430103437.4140-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210430103437.4140-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags.  But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses.  So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.

We cannot tell a priori whether or not a given scalar access is aligned,
therefore we must at least check.  Use mte_probe_int, which is already
set up for checking multiple granules.

Buglink: https://bugs.launchpad.net/bugs/1921948
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/mte_helper.c | 109 +++++++++++++---------------------------
 1 file changed, 35 insertions(+), 74 deletions(-)

diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 2b5331f8dbc..0ee0397eb26 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -617,80 +617,6 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
     }
 }
 
-/*
- * Perform an MTE checked access for a single logical or atomic access.
- */
-static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
-                           uintptr_t ra, int bit55)
-{
-    int mem_tag, mmu_idx, ptr_tag, size;
-    MMUAccessType type;
-    uint8_t *mem;
-
-    ptr_tag = allocation_tag_from_addr(ptr);
-
-    if (tcma_check(desc, bit55, ptr_tag)) {
-        return true;
-    }
-
-    mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
-    type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD;
-    size = FIELD_EX32(desc, MTEDESC, ESIZE);
-
-    mem = allocation_tag_mem(env, mmu_idx, ptr, type, size,
-                             MMU_DATA_LOAD, 1, ra);
-    if (!mem) {
-        return true;
-    }
-
-    mem_tag = load_tag1(ptr, mem);
-    return ptr_tag == mem_tag;
-}
-
-/*
- * No-fault version of mte_check1, to be used by SVE for MemSingleNF.
- * Returns false if the access is Checked and the check failed.  This
- * is only intended to probe the tag -- the validity of the page must
- * be checked beforehand.
- */
-bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr)
-{
-    int bit55 = extract64(ptr, 55, 1);
-
-    /* If TBI is disabled, the access is unchecked. */
-    if (unlikely(!tbi_check(desc, bit55))) {
-        return true;
-    }
-
-    return mte_probe1_int(env, desc, ptr, 0, bit55);
-}
-
-uint64_t mte_check1(CPUARMState *env, uint32_t desc,
-                    uint64_t ptr, uintptr_t ra)
-{
-    int bit55 = extract64(ptr, 55, 1);
-
-    /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */
-    if (unlikely(!tbi_check(desc, bit55))) {
-        return ptr;
-    }
-
-    if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
-        mte_check_fail(env, desc, ptr, ra);
-    }
-
-    return useronly_clean_ptr(ptr);
-}
-
-uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr)
-{
-    return mte_check1(env, desc, ptr, GETPC());
-}
-
-/*
- * Perform an MTE checked access for multiple logical accesses.
- */
-
 /**
  * checkN:
  * @tag: tag memory to test
@@ -882,6 +808,41 @@ uint64_t HELPER(mte_checkN)(CPUARMState *env, uint32_t desc, uint64_t ptr)
     return mte_checkN(env, desc, ptr, GETPC());
 }
 
+uint64_t mte_check1(CPUARMState *env, uint32_t desc,
+                    uint64_t ptr, uintptr_t ra)
+{
+    uint64_t fault;
+    uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE);
+    int ret = mte_probe_int(env, desc, ptr, ra, total, &fault);
+
+    if (unlikely(ret == 0)) {
+        mte_check_fail(env, desc, fault, ra);
+    } else if (ret < 0) {
+        return ptr;
+    }
+    return useronly_clean_ptr(ptr);
+}
+
+uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr)
+{
+    return mte_check1(env, desc, ptr, GETPC());
+}
+
+/*
+ * No-fault version of mte_check1, to be used by SVE for MemSingleNF.
+ * Returns false if the access is Checked and the check failed.  This
+ * is only intended to probe the tag -- the validity of the page must
+ * be checked beforehand.
+ */
+bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr)
+{
+    uint64_t fault;
+    uint32_t total = FIELD_EX32(desc, MTEDESC, ESIZE);
+    int ret = mte_probe_int(env, desc, ptr, 0, total, &fault);
+
+    return ret != 0;
+}
+
 /*
  * Perform an MTE checked access for DC_ZVA.
  */
-- 
2.20.1



  parent reply	other threads:[~2021-04-30 10:39 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-30 10:33 [PULL 00/43] target-arm queue Peter Maydell
2021-04-30 10:33 ` [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule Peter Maydell
2021-04-30 10:33 ` [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111 Peter Maydell
2021-04-30 10:33 ` [PULL 03/43] target/arm: Fix mte_checkN Peter Maydell
2021-04-30 10:33 ` [PULL 04/43] target/arm: Split out mte_probe_int Peter Maydell
2021-04-30 10:33 ` Peter Maydell [this message]
2021-04-30 10:34 ` [PULL 06/43] test/tcg/aarch64: Add mte-5 Peter Maydell
2021-04-30 10:34 ` [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 Peter Maydell
2021-04-30 10:34 ` [PULL 08/43] target/arm: Merge mte_check1, mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 09/43] target/arm: Rename mte_probe1 to mte_probe Peter Maydell
2021-04-30 10:34 ` [PULL 10/43] target/arm: Simplify sve mte checking Peter Maydell
2021-04-30 10:34 ` [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN Peter Maydell
2021-04-30 10:34 ` [PULL 12/43] target/arm: Fix decode of align in VLDST_single Peter Maydell
2021-04-30 10:34 ` [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B Peter Maydell
2021-04-30 10:34 ` [PULL 14/43] target/arm: Rename TBFLAG_ANY, PSTATE_SS Peter Maydell
2021-04-30 10:34 ` [PULL 15/43] target/arm: Add wrapper macros for accessing tbflags Peter Maydell
2021-04-30 10:34 ` [PULL 16/43] target/arm: Introduce CPUARMTBFlags Peter Maydell
2021-04-30 10:34 ` [PULL 17/43] target/arm: Move mode specific TB flags to tb->cs_base Peter Maydell
2021-04-30 10:34 ` [PULL 18/43] target/arm: Move TBFLAG_AM32 bits to the top Peter Maydell
2021-04-30 10:34 ` [PULL 19/43] target/arm: Move TBFLAG_ANY bits to the bottom Peter Maydell
2021-04-30 10:34 ` [PULL 20/43] target/arm: Add ALIGN_MEM to TBFLAG_ANY Peter Maydell
2021-04-30 10:34 ` [PULL 21/43] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 22/43] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Peter Maydell
2021-04-30 10:34 ` [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Peter Maydell
2021-04-30 10:34 ` [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Peter Maydell
2021-04-30 10:34 ` [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD Peter Maydell
2021-04-30 10:34 ` [PULL 26/43] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Peter Maydell
2021-04-30 10:34 ` [PULL 27/43] target/arm: Enforce alignment for LDM/STM Peter Maydell
2021-04-30 10:34 ` [PULL 28/43] target/arm: Enforce alignment for RFE Peter Maydell
2021-04-30 10:34 ` [PULL 29/43] target/arm: Enforce alignment for SRS Peter Maydell
2021-04-30 10:34 ` [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM Peter Maydell
2021-04-30 10:34 ` [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR Peter Maydell
2021-04-30 10:34 ` [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes) Peter Maydell
2021-04-30 10:34 ` [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store Peter Maydell
2021-04-30 10:34 ` [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel Peter Maydell
2021-04-30 10:34 ` [PULL 38/43] target/arm: Use MemOp for size + endian in aa64 vector ld/st Peter Maydell
2021-04-30 10:34 ` [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Peter Maydell
2021-04-30 10:34 ` [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Peter Maydell
2021-04-30 10:34 ` [PULL 41/43] target/arm: Enforce alignment for sve LD1R Peter Maydell
2021-04-30 10:34 ` [PULL 42/43] hw: add compat machines for 6.1 Peter Maydell
2021-04-30 10:34 ` [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows Peter Maydell
2021-04-30 11:18 ` [PULL 00/43] target-arm queue no-reply
2021-04-30 12:45 ` Peter Maydell

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