From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v6 69/82] target/arm: Share table of sve load functions
Date: Fri, 30 Apr 2021 13:25:57 -0700 [thread overview]
Message-ID: <20210430202610.1136687-70-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210430202610.1136687-1-richard.henderson@linaro.org>
The table used by do_ldrq is a subset of the table used by do_ld_zpa;
we can share them by passing dtype instead of msz to do_ldrq.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 254 ++++++++++++++++++-------------------
1 file changed, 126 insertions(+), 128 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index a949f53f4a..ca393164bc 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5153,128 +5153,130 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
tcg_temp_free_i32(t_desc);
}
+/* Indexed by [mte][be][dtype][nreg] */
+static gen_helper_gvec_mem * const ldr_fns[2][2][16][4] = {
+ { /* mte inactive, little-endian */
+ { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
+ gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
+ { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r,
+ gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r },
+ { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r,
+ gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r },
+ { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r,
+ gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } },
+
+ /* mte inactive, big-endian */
+ { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
+ gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
+ { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r,
+ gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r },
+ { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r,
+ gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r },
+ { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
+ { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r,
+ gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } },
+
+ { /* mte active, little-endian */
+ { { gen_helper_sve_ld1bb_r_mte,
+ gen_helper_sve_ld2bb_r_mte,
+ gen_helper_sve_ld3bb_r_mte,
+ gen_helper_sve_ld4bb_r_mte },
+ { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hh_le_r_mte,
+ gen_helper_sve_ld2hh_le_r_mte,
+ gen_helper_sve_ld3hh_le_r_mte,
+ gen_helper_sve_ld4hh_le_r_mte },
+ { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1ss_le_r_mte,
+ gen_helper_sve_ld2ss_le_r_mte,
+ gen_helper_sve_ld3ss_le_r_mte,
+ gen_helper_sve_ld4ss_le_r_mte },
+ { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1dd_le_r_mte,
+ gen_helper_sve_ld2dd_le_r_mte,
+ gen_helper_sve_ld3dd_le_r_mte,
+ gen_helper_sve_ld4dd_le_r_mte } },
+
+ /* mte active, big-endian */
+ { { gen_helper_sve_ld1bb_r_mte,
+ gen_helper_sve_ld2bb_r_mte,
+ gen_helper_sve_ld3bb_r_mte,
+ gen_helper_sve_ld4bb_r_mte },
+ { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hh_be_r_mte,
+ gen_helper_sve_ld2hh_be_r_mte,
+ gen_helper_sve_ld3hh_be_r_mte,
+ gen_helper_sve_ld4hh_be_r_mte },
+ { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1ss_be_r_mte,
+ gen_helper_sve_ld2ss_be_r_mte,
+ gen_helper_sve_ld3ss_be_r_mte,
+ gen_helper_sve_ld4ss_be_r_mte },
+ { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL },
+
+ { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
+ { gen_helper_sve_ld1dd_be_r_mte,
+ gen_helper_sve_ld2dd_be_r_mte,
+ gen_helper_sve_ld3dd_be_r_mte,
+ gen_helper_sve_ld4dd_be_r_mte } } },
+};
+
static void do_ld_zpa(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int dtype, int nreg)
{
- static gen_helper_gvec_mem * const fns[2][2][16][4] = {
- { /* mte inactive, little-endian */
- { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
- gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
- { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1sds_le_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hh_le_r, gen_helper_sve_ld2hh_le_r,
- gen_helper_sve_ld3hh_le_r, gen_helper_sve_ld4hh_le_r },
- { gen_helper_sve_ld1hsu_le_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hdu_le_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1hds_le_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hss_le_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld2ss_le_r,
- gen_helper_sve_ld3ss_le_r, gen_helper_sve_ld4ss_le_r },
- { gen_helper_sve_ld1sdu_le_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1dd_le_r, gen_helper_sve_ld2dd_le_r,
- gen_helper_sve_ld3dd_le_r, gen_helper_sve_ld4dd_le_r } },
-
- /* mte inactive, big-endian */
- { { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
- gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
- { gen_helper_sve_ld1bhu_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bsu_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bdu_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1sds_be_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hh_be_r, gen_helper_sve_ld2hh_be_r,
- gen_helper_sve_ld3hh_be_r, gen_helper_sve_ld4hh_be_r },
- { gen_helper_sve_ld1hsu_be_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hdu_be_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1hds_be_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1hss_be_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld2ss_be_r,
- gen_helper_sve_ld3ss_be_r, gen_helper_sve_ld4ss_be_r },
- { gen_helper_sve_ld1sdu_be_r, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1bds_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bss_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1bhs_r, NULL, NULL, NULL },
- { gen_helper_sve_ld1dd_be_r, gen_helper_sve_ld2dd_be_r,
- gen_helper_sve_ld3dd_be_r, gen_helper_sve_ld4dd_be_r } } },
-
- { /* mte active, little-endian */
- { { gen_helper_sve_ld1bb_r_mte,
- gen_helper_sve_ld2bb_r_mte,
- gen_helper_sve_ld3bb_r_mte,
- gen_helper_sve_ld4bb_r_mte },
- { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1sds_le_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hh_le_r_mte,
- gen_helper_sve_ld2hh_le_r_mte,
- gen_helper_sve_ld3hh_le_r_mte,
- gen_helper_sve_ld4hh_le_r_mte },
- { gen_helper_sve_ld1hsu_le_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hdu_le_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1hds_le_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hss_le_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1ss_le_r_mte,
- gen_helper_sve_ld2ss_le_r_mte,
- gen_helper_sve_ld3ss_le_r_mte,
- gen_helper_sve_ld4ss_le_r_mte },
- { gen_helper_sve_ld1sdu_le_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1dd_le_r_mte,
- gen_helper_sve_ld2dd_le_r_mte,
- gen_helper_sve_ld3dd_le_r_mte,
- gen_helper_sve_ld4dd_le_r_mte } },
-
- /* mte active, big-endian */
- { { gen_helper_sve_ld1bb_r_mte,
- gen_helper_sve_ld2bb_r_mte,
- gen_helper_sve_ld3bb_r_mte,
- gen_helper_sve_ld4bb_r_mte },
- { gen_helper_sve_ld1bhu_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bsu_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bdu_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1sds_be_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hh_be_r_mte,
- gen_helper_sve_ld2hh_be_r_mte,
- gen_helper_sve_ld3hh_be_r_mte,
- gen_helper_sve_ld4hh_be_r_mte },
- { gen_helper_sve_ld1hsu_be_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hdu_be_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1hds_be_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1hss_be_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1ss_be_r_mte,
- gen_helper_sve_ld2ss_be_r_mte,
- gen_helper_sve_ld3ss_be_r_mte,
- gen_helper_sve_ld4ss_be_r_mte },
- { gen_helper_sve_ld1sdu_be_r_mte, NULL, NULL, NULL },
-
- { gen_helper_sve_ld1bds_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bss_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1bhs_r_mte, NULL, NULL, NULL },
- { gen_helper_sve_ld1dd_be_r_mte,
- gen_helper_sve_ld2dd_be_r_mte,
- gen_helper_sve_ld3dd_be_r_mte,
- gen_helper_sve_ld4dd_be_r_mte } } },
- };
gen_helper_gvec_mem *fn
- = fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg];
+ = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg];
/*
* While there are holes in the table, they are not
@@ -5512,14 +5514,8 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
return true;
}
-static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
+static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
{
- static gen_helper_gvec_mem * const fns[2][4] = {
- { gen_helper_sve_ld1bb_r, gen_helper_sve_ld1hh_le_r,
- gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld1dd_le_r },
- { gen_helper_sve_ld1bb_r, gen_helper_sve_ld1hh_be_r,
- gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld1dd_be_r },
- };
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 t_desc;
@@ -5551,7 +5547,9 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
t_pg = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_pg, cpu_env, poff);
- fns[s->be_data == MO_BE][msz](cpu_env, t_pg, addr, t_desc);
+ gen_helper_gvec_mem *fn
+ = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
+ fn(cpu_env, t_pg, addr, t_desc);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i32(t_desc);
@@ -5573,7 +5571,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a)
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz);
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
- do_ldrq(s, a->rd, a->pg, addr, msz);
+ do_ldrq(s, a->rd, a->pg, addr, a->dtype);
}
return true;
}
@@ -5583,7 +5581,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a)
if (sve_access_check(s)) {
TCGv_i64 addr = new_tmp_a64(s);
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16);
- do_ldrq(s, a->rd, a->pg, addr, dtype_msz(a->dtype));
+ do_ldrq(s, a->rd, a->pg, addr, a->dtype);
}
return true;
}
--
2.25.1
next prev parent reply other threads:[~2021-04-30 21:35 UTC|newest]
Thread overview: 184+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 20:24 [PATCH v6 00/82] target/arm: Implement SVE2 Richard Henderson
2021-04-30 20:24 ` [PATCH v6 01/82] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Richard Henderson
2021-05-11 7:55 ` Peter Maydell
2021-05-11 17:20 ` Richard Henderson
2021-04-30 20:24 ` [PATCH v6 02/82] target/arm: Implement SVE2 Integer Multiply - Unpredicated Richard Henderson
2021-05-11 8:00 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 03/82] target/arm: Implement SVE2 integer pairwise add and accumulate long Richard Henderson
2021-05-11 8:02 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 04/82] target/arm: Implement SVE2 integer unary operations (predicated) Richard Henderson
2021-05-11 8:10 ` Peter Maydell
2021-05-11 17:22 ` Richard Henderson
2021-04-30 20:24 ` [PATCH v6 05/82] target/arm: Split out saturating/rounding shifts from neon Richard Henderson
2021-05-11 8:36 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 06/82] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) Richard Henderson
2021-05-11 8:43 ` Peter Maydell
2021-05-11 15:40 ` Richard Henderson
2021-05-11 15:56 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 07/82] target/arm: Implement SVE2 integer halving add/subtract (predicated) Richard Henderson
2021-05-11 8:45 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 08/82] target/arm: Implement SVE2 integer pairwise arithmetic Richard Henderson
2021-05-11 8:58 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 09/82] target/arm: Implement SVE2 saturating add/subtract (predicated) Richard Henderson
2021-05-11 9:07 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 10/82] target/arm: Implement SVE2 integer add/subtract long Richard Henderson
2021-05-11 9:11 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 11/82] target/arm: Implement SVE2 integer add/subtract interleaved long Richard Henderson
2021-05-11 9:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 12/82] target/arm: Implement SVE2 integer add/subtract wide Richard Henderson
2021-05-11 9:14 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 13/82] target/arm: Implement SVE2 integer multiply long Richard Henderson
2021-05-11 12:21 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 14/82] target/arm: Implement PMULLB and PMULLT Richard Henderson
2021-05-11 12:29 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 15/82] target/arm: Implement SVE2 bitwise shift left long Richard Henderson
2021-05-11 12:40 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 16/82] target/arm: Implement SVE2 bitwise exclusive-or interleaved Richard Henderson
2021-05-11 12:43 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 17/82] target/arm: Implement SVE2 bitwise permute Richard Henderson
2021-05-11 12:58 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 18/82] target/arm: Implement SVE2 complex integer add Richard Henderson
2021-05-11 13:02 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 19/82] target/arm: Implement SVE2 integer absolute difference and accumulate long Richard Henderson
2021-05-11 15:27 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 20/82] target/arm: Implement SVE2 integer add/subtract long with carry Richard Henderson
2021-05-11 15:48 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 21/82] target/arm: Implement SVE2 bitwise shift right and accumulate Richard Henderson
2021-05-11 15:57 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 22/82] target/arm: Implement SVE2 bitwise shift and insert Richard Henderson
2021-05-11 15:58 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 23/82] target/arm: Implement SVE2 integer absolute difference and accumulate Richard Henderson
2021-05-11 15:59 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 24/82] target/arm: Implement SVE2 saturating extract narrow Richard Henderson
2021-05-11 16:08 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 25/82] target/arm: Implement SVE2 floating-point pairwise Richard Henderson
2021-05-11 16:09 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 26/82] target/arm: Implement SVE2 SHRN, RSHRN Richard Henderson
2021-05-12 8:52 ` Peter Maydell
2021-05-12 16:07 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 27/82] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN Richard Henderson
2021-05-12 8:54 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 28/82] target/arm: Implement SVE2 UQSHRN, UQRSHRN Richard Henderson
2021-05-12 8:56 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 29/82] target/arm: Implement SVE2 SQSHRN, SQRSHRN Richard Henderson
2021-05-12 8:59 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 30/82] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS Richard Henderson
2021-05-12 9:07 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 31/82] target/arm: Implement SVE2 WHILERW, WHILEWR Richard Henderson
2021-05-12 14:06 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 32/82] target/arm: Implement SVE2 bitwise ternary operations Richard Henderson
2021-05-12 14:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 33/82] target/arm: Implement SVE2 MATCH, NMATCH Richard Henderson
2021-04-30 20:25 ` [PATCH v6 34/82] target/arm: Implement SVE2 saturating multiply-add long Richard Henderson
2021-05-12 14:21 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 35/82] target/arm: Implement SVE2 saturating multiply-add high Richard Henderson
2021-05-12 15:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 36/82] target/arm: Implement SVE2 integer multiply-add long Richard Henderson
2021-05-12 15:13 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 37/82] target/arm: Implement SVE2 complex integer multiply-add Richard Henderson
2021-05-12 15:20 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 38/82] target/arm: Implement SVE2 ADDHNB, ADDHNT Richard Henderson
2021-05-12 15:23 ` Peter Maydell
2021-05-12 16:17 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 39/82] target/arm: Implement SVE2 RADDHNB, RADDHNT Richard Henderson
2021-05-12 15:24 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT Richard Henderson
2021-05-12 15:24 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 41/82] target/arm: Implement SVE2 RSUBHNB, RSUBHNT Richard Henderson
2021-05-12 15:25 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 42/82] target/arm: Implement SVE2 HISTCNT, HISTSEG Richard Henderson
2021-05-13 10:22 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 43/82] target/arm: Implement SVE2 XAR Richard Henderson
2021-05-13 10:27 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 44/82] target/arm: Implement SVE2 scatter store insns Richard Henderson
2021-05-13 10:31 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 45/82] target/arm: Implement SVE2 gather load insns Richard Henderson
2021-05-13 10:33 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 46/82] target/arm: Implement SVE2 FMMLA Richard Henderson
2021-05-13 10:38 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 47/82] target/arm: Implement SVE2 SPLICE, EXT Richard Henderson
2021-05-13 10:41 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 48/82] target/arm: Pass separate addend to {U, S}DOT helpers Richard Henderson
2021-05-13 10:47 ` Peter Maydell
2021-05-14 16:33 ` Richard Henderson
2021-05-14 16:35 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 49/82] target/arm: Pass separate addend to FCMLA helpers Richard Henderson
2021-04-30 20:25 ` [PATCH v6 50/82] target/arm: Split out formats for 2 vectors + 1 index Richard Henderson
2021-05-13 10:49 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 51/82] target/arm: Split out formats for 3 " Richard Henderson
2021-05-13 10:53 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 52/82] target/arm: Implement SVE2 integer multiply (indexed) Richard Henderson
2021-05-13 12:31 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 53/82] target/arm: Implement SVE2 integer multiply-add (indexed) Richard Henderson
2021-05-13 12:33 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 54/82] target/arm: Implement SVE2 saturating multiply-add high (indexed) Richard Henderson
2021-05-13 12:35 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 55/82] target/arm: Implement SVE2 saturating multiply-add (indexed) Richard Henderson
2021-05-13 12:42 ` Peter Maydell
2021-05-14 18:17 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 56/82] target/arm: Implement SVE2 saturating multiply (indexed) Richard Henderson
2021-05-13 12:45 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 57/82] target/arm: Implement SVE2 signed saturating doubling multiply high Richard Henderson
2021-05-13 12:48 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 58/82] target/arm: Implement SVE2 saturating multiply high (indexed) Richard Henderson
2021-05-13 12:51 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 59/82] target/arm: Implement SVE mixed sign dot product (indexed) Richard Henderson
2021-05-13 12:57 ` Peter Maydell
2021-05-14 18:47 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 60/82] target/arm: Implement SVE mixed sign dot product Richard Henderson
2021-05-13 13:01 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 61/82] target/arm: Implement SVE2 crypto unary operations Richard Henderson
2021-05-13 13:02 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 62/82] target/arm: Implement SVE2 crypto destructive binary operations Richard Henderson
2021-05-13 13:04 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 63/82] target/arm: Implement SVE2 crypto constructive " Richard Henderson
2021-05-13 13:52 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 64/82] target/arm: Implement SVE2 TBL, TBX Richard Henderson
2021-05-13 13:59 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 65/82] target/arm: Implement SVE2 FCVTNT Richard Henderson
2021-05-13 14:01 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 66/82] target/arm: Implement SVE2 FCVTLT Richard Henderson
2021-05-13 14:03 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX Richard Henderson
2021-05-13 14:06 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 68/82] target/arm: Implement SVE2 FLOGB Richard Henderson
2021-05-13 14:18 ` Peter Maydell
2021-05-15 16:14 ` Richard Henderson
2021-04-30 20:25 ` Richard Henderson [this message]
2021-05-13 14:25 ` [PATCH v6 69/82] target/arm: Share table of sve load functions Peter Maydell
2021-05-15 16:25 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 70/82] target/arm: Implement SVE2 LD1RO Richard Henderson
2021-05-13 16:41 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 71/82] target/arm: Implement 128-bit ZIP, UZP, TRN Richard Henderson
2021-05-13 16:48 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate Richard Henderson
2021-05-13 16:57 ` Peter Maydell
2021-05-15 16:53 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 73/82] target/arm: Implement SVE2 fp multiply-add long Richard Henderson
2021-05-13 17:04 ` Peter Maydell
2021-05-15 17:09 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 74/82] target/arm: Implement aarch64 SUDOT, USDOT Richard Henderson
2021-05-13 17:09 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 75/82] target/arm: Split out do_neon_ddda_fpst Richard Henderson
2021-05-13 17:13 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 76/82] target/arm: Remove unused fpst from VDOT_scalar Richard Henderson
2021-05-13 17:18 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 77/82] target/arm: Fix decode for VDOT (indexed) Richard Henderson
2021-05-13 19:25 ` Peter Maydell
2021-05-15 17:13 ` Richard Henderson
2021-05-16 16:09 ` Peter Maydell
2021-05-17 15:48 ` Richard Henderson
2021-05-15 17:20 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 78/82] target/arm: Split decode of VSDOT and VUDOT Richard Henderson
2021-05-13 19:27 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 79/82] target/arm: Implement aarch32 VSUDOT, VUSDOT Richard Henderson
2021-05-13 19:32 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 80/82] target/arm: Implement integer matrix multiply accumulate Richard Henderson
2021-05-13 19:49 ` Peter Maydell
2021-05-14 16:58 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 81/82] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions Richard Henderson
2021-05-13 19:33 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 82/82] target/arm: Enable SVE2 " Richard Henderson
2021-05-13 19:35 ` Peter Maydell
2021-05-14 17:21 ` Richard Henderson
2021-05-13 19:49 ` [PATCH v6 00/82] target/arm: Implement SVE2 Peter Maydell
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