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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Fabiano Rosas" <farosas@linux.ibm.com>,
	"Cédric Le Goater" <clg@fr.ibm.com>,
	qemu-devel@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model
Date: Sat,  1 May 2021 17:24:33 +1000	[thread overview]
Message-ID: <20210501072436.145444-1-npiggin@gmail.com> (raw)

Here are the last 2 patches of this series rebased on the ppc-for-6.1
tree.  I've tidied up the comments and control flow around the reserved
values of AIL, so different behaviours/reasons are treated individually
which hopefully addresses David's comments.

On real hardware, setting LPCR[AIL] to a reserved value (e.g., 1 on
POWER9) causes the register to retain that value but it's treated like
0, which matches what the patch does.

Thanks,
Nick

Nicholas Piggin (2):
  target/ppc: rework AIL logic in interrupt delivery
  target/ppc: Add POWER10 exception model

 hw/ppc/spapr_hcall.c            |   8 +-
 target/ppc/cpu-qom.h            |   2 +
 target/ppc/cpu.h                |  13 +-
 target/ppc/excp_helper.c        | 217 +++++++++++++++++++++++---------
 target/ppc/translate.c          |   3 +-
 target/ppc/translate_init.c.inc |   4 +-
 6 files changed, 171 insertions(+), 76 deletions(-)

-- 
2.23.0



             reply	other threads:[~2021-05-01  7:26 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-01  7:24 Nicholas Piggin [this message]
2021-05-01  7:24 ` [PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin
2021-05-03  3:41   ` David Gibson
2021-05-01  7:24 ` [PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin
2021-05-03  3:42   ` David Gibson

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