From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Taylor Simpson <tsimpson@quicinc.com>
Subject: [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time
Date: Sat, 1 May 2021 11:43:04 -0700 [thread overview]
Message-ID: <20210501184324.1338186-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210501184324.1338186-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
Multiple writes to the same preg are and'ed together. Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.
Test added to tests/tcg/hexagon/misc.c
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/translate.h | 2 ++
target/hexagon/genptr.c | 22 +++++++++++++++-------
target/hexagon/translate.c | 9 +++++++--
tests/tcg/hexagon/misc.c | 19 +++++++++++++++++++
target/hexagon/gen_tcg_funcs.py | 2 +-
5 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 12506c8caf..0ecfbd7d52 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -34,6 +34,7 @@ typedef struct DisasContext {
DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
int preg_log[PRED_WRITES_MAX];
int preg_log_idx;
+ DECLARE_BITMAP(pregs_written, NUM_PREGS);
uint8_t store_width[STORES_MAX];
uint8_t s1_store_processed;
} DisasContext;
@@ -60,6 +61,7 @@ static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
{
ctx->preg_log[ctx->preg_log_idx] = pnum;
ctx->preg_log_idx++;
+ set_bit(pnum, ctx->pregs_written);
}
static inline bool is_preloaded(DisasContext *ctx, int num)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 07d970fc6c..6b74344795 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -119,20 +119,28 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
#endif
}
-static inline void gen_log_pred_write(int pnum, TCGv val)
+static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
{
TCGv zero = tcg_const_tl(0);
TCGv base_val = tcg_temp_new();
TCGv and_val = tcg_temp_new();
TCGv pred_written = tcg_temp_new();
- /* Multiple writes to the same preg are and'ed together */
tcg_gen_andi_tl(base_val, val, 0xff);
- tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]);
- tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum);
- tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum],
- pred_written, zero,
- and_val, base_val);
+
+ /*
+ * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
+ *
+ * Multiple writes to the same preg are and'ed together
+ * If this is the first predicate write in the packet, do a
+ * straight assignment. Otherwise, do an and.
+ */
+ if (!test_bit(pnum, ctx->pregs_written)) {
+ tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val);
+ } else {
+ tcg_gen_and_tl(hex_new_pred_value[pnum],
+ hex_new_pred_value[pnum], base_val);
+ }
tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
tcg_temp_free(zero);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 9f2a531969..49ec8b76ed 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -172,6 +172,7 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
ctx->reg_log_idx = 0;
bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
ctx->preg_log_idx = 0;
+ bitmap_zero(ctx->pregs_written, NUM_PREGS);
for (i = 0; i < STORES_MAX; i++) {
ctx->store_width[i] = 0;
}
@@ -226,7 +227,7 @@ static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn,
}
}
-static void mark_implicit_writes(DisasContext *ctx, Insn *insn)
+static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
{
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
@@ -235,7 +236,10 @@ static void mark_implicit_writes(DisasContext *ctx, Insn *insn)
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
+}
+static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
+{
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
@@ -246,8 +250,9 @@ static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
Insn *insn, Packet *pkt)
{
if (insn->generate) {
- mark_implicit_writes(ctx, insn);
+ mark_implicit_reg_writes(ctx, insn);
insn->generate(env, ctx, insn, pkt);
+ mark_implicit_pred_writes(ctx, insn);
} else {
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
}
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index 458759f7b1..e5d78b471f 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -264,6 +264,22 @@ static long long creg_pair(int x, int y)
return retval;
}
+/* Check that predicates are auto-and'ed in a packet */
+static int auto_and(void)
+{
+ int retval;
+ asm ("r5 = #1\n\t"
+ "{\n\t"
+ " p0 = cmp.eq(r1, #1)\n\t"
+ " p0 = cmp.eq(r1, #2)\n\t"
+ "}\n\t"
+ "%0 = p0\n\t"
+ : "=r"(retval)
+ :
+ : "r5", "p0");
+ return retval;
+}
+
int main()
{
@@ -375,6 +391,9 @@ int main()
res = test_clrtnew(2, 7);
check(res, 7);
+ res = auto_and();
+ check(res, 0);
+
puts(err ? "FAIL" : "PASS");
return err;
}
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index db9f663a77..7ceb25b5f6 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -316,7 +316,7 @@ def genptr_dst_write(f, tag, regtype, regid):
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"d", "e", "x"}):
- f.write(" gen_log_pred_write(%s%sN, %s%sV);\n" % \
+ f.write(" gen_log_pred_write(ctx, %s%sN, %s%sV);\n" % \
(regtype, regid, regtype, regid))
f.write(" ctx_log_pred_write(ctx, %s%sN);\n" % \
(regtype, regid))
--
2.25.1
next prev parent reply other threads:[~2021-05-01 18:50 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-01 18:42 [PULL 00/31] target/hexagon patch queue Richard Henderson
2021-05-01 18:42 ` [PULL 01/31] target/hexagon: translation changes Richard Henderson
2021-05-01 18:42 ` [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots Richard Henderson
2021-05-01 18:42 ` [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM Richard Henderson
2021-05-01 18:42 ` [PULL 04/31] target/hexagon: fix typo in comment Richard Henderson
2021-05-01 18:42 ` [PULL 05/31] target/hexagon: remove unnecessary semicolons Richard Henderson
2021-05-01 18:42 ` [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup Richard Henderson
2021-05-01 18:43 ` [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Richard Henderson
2021-05-01 18:43 ` [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives Richard Henderson
2021-05-01 18:43 ` [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu Richard Henderson
2021-05-01 18:43 ` [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Richard Henderson
2021-05-01 18:43 ` Richard Henderson [this message]
2021-05-01 18:43 ` [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate Richard Henderson
2021-05-01 18:43 ` [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function Richard Henderson
2021-05-01 18:43 ` [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes Richard Henderson
2021-05-01 18:43 ` [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess Richard Henderson
2021-05-01 18:43 ` [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Richard Henderson
2021-05-01 18:43 ` [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions Richard Henderson
2021-05-01 18:43 ` [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics Richard Henderson
2021-05-01 18:43 ` [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition Richard Henderson
2021-05-01 18:43 ` [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Richard Henderson
2021-05-01 18:43 ` [PULL 21/31] Hexagon (target/hexagon) compile all debug code Richard Henderson
2021-05-01 18:43 ` [PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction Richard Henderson
2021-05-01 18:43 ` [PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta Richard Henderson
2021-05-01 18:43 ` [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh) Richard Henderson
2021-05-01 18:43 ` [PULL 25/31] Hexagon (target/hexagon) add A6_vminub_RdP Richard Henderson
2021-05-01 18:43 ` [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Richard Henderson
2021-05-01 18:43 ` [PULL 27/31] Hexagon (target/hexagon) circular addressing Richard Henderson
2021-05-01 18:43 ` [PULL 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing Richard Henderson
2021-05-01 18:43 ` [PULL 29/31] Hexagon (target/hexagon) load and unpack bytes instructions Richard Henderson
2021-05-01 18:43 ` [PULL 30/31] Hexagon (target/hexagon) load into shifted register instructions Richard Henderson
2021-05-01 18:43 ` [PULL 31/31] Hexagon (target/hexagon) CABAC decode bin Richard Henderson
2021-05-01 20:40 ` [PULL 00/31] target/hexagon patch queue Peter Maydell
2021-05-01 22:31 ` Richard Henderson
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