From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Taylor Simpson <tsimpson@quicinc.com>
Subject: [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
Date: Sat, 1 May 2021 11:43:09 -0700 [thread overview]
Message-ID: <20210501184324.1338186-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210501184324.1338186-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-12-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/arch.c | 28 +++++++++++-----------------
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c
index bb51f19a3d..40b6e3d0c0 100644
--- a/target/hexagon/arch.c
+++ b/target/hexagon/arch.c
@@ -143,12 +143,6 @@ void arch_fpop_end(CPUHexagonState *env)
}
}
-static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_status)
-{
- float32 b = make_float32((SF_BIAS + p) << SF_MANTBITS);
- return float32_mul(a, b, fp_status);
-}
-
int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,
float_status *fp_status)
{
@@ -217,22 +211,22 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,
if ((n_exp - d_exp + SF_BIAS) <= SF_MANTBITS) {
/* Near quotient underflow / inexact Q */
PeV = 0x80;
- RtV = float32_mul_pow2(RtV, -64, fp_status);
- RsV = float32_mul_pow2(RsV, 64, fp_status);
+ RtV = float32_scalbn(RtV, -64, fp_status);
+ RsV = float32_scalbn(RsV, 64, fp_status);
} else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) {
/* Near quotient overflow */
PeV = 0x40;
- RtV = float32_mul_pow2(RtV, 32, fp_status);
- RsV = float32_mul_pow2(RsV, -32, fp_status);
+ RtV = float32_scalbn(RtV, 32, fp_status);
+ RsV = float32_scalbn(RsV, -32, fp_status);
} else if (n_exp <= SF_MANTBITS + 2) {
- RtV = float32_mul_pow2(RtV, 64, fp_status);
- RsV = float32_mul_pow2(RsV, 64, fp_status);
+ RtV = float32_scalbn(RtV, 64, fp_status);
+ RsV = float32_scalbn(RsV, 64, fp_status);
} else if (d_exp <= 1) {
- RtV = float32_mul_pow2(RtV, 32, fp_status);
- RsV = float32_mul_pow2(RsV, 32, fp_status);
+ RtV = float32_scalbn(RtV, 32, fp_status);
+ RsV = float32_scalbn(RsV, 32, fp_status);
} else if (d_exp > 252) {
- RtV = float32_mul_pow2(RtV, -32, fp_status);
- RsV = float32_mul_pow2(RsV, -32, fp_status);
+ RtV = float32_scalbn(RtV, -32, fp_status);
+ RsV = float32_scalbn(RsV, -32, fp_status);
}
RdV = 0;
ret = 1;
@@ -274,7 +268,7 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust,
/* Basic checks passed */
r_exp = float32_getexp(RsV);
if (r_exp <= 24) {
- RsV = float32_mul_pow2(RsV, 64, fp_status);
+ RsV = float32_scalbn(RsV, 64, fp_status);
PeV = 0xe0;
}
RdV = 0;
--
2.25.1
next prev parent reply other threads:[~2021-05-01 18:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-01 18:42 [PULL 00/31] target/hexagon patch queue Richard Henderson
2021-05-01 18:42 ` [PULL 01/31] target/hexagon: translation changes Richard Henderson
2021-05-01 18:42 ` [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots Richard Henderson
2021-05-01 18:42 ` [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM Richard Henderson
2021-05-01 18:42 ` [PULL 04/31] target/hexagon: fix typo in comment Richard Henderson
2021-05-01 18:42 ` [PULL 05/31] target/hexagon: remove unnecessary semicolons Richard Henderson
2021-05-01 18:42 ` [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup Richard Henderson
2021-05-01 18:43 ` [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Richard Henderson
2021-05-01 18:43 ` [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives Richard Henderson
2021-05-01 18:43 ` [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu Richard Henderson
2021-05-01 18:43 ` [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Richard Henderson
2021-05-01 18:43 ` [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Richard Henderson
2021-05-01 18:43 ` [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate Richard Henderson
2021-05-01 18:43 ` [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function Richard Henderson
2021-05-01 18:43 ` [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes Richard Henderson
2021-05-01 18:43 ` [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess Richard Henderson
2021-05-01 18:43 ` Richard Henderson [this message]
2021-05-01 18:43 ` [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions Richard Henderson
2021-05-01 18:43 ` [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics Richard Henderson
2021-05-01 18:43 ` [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition Richard Henderson
2021-05-01 18:43 ` [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Richard Henderson
2021-05-01 18:43 ` [PULL 21/31] Hexagon (target/hexagon) compile all debug code Richard Henderson
2021-05-01 18:43 ` [PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction Richard Henderson
2021-05-01 18:43 ` [PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta Richard Henderson
2021-05-01 18:43 ` [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh) Richard Henderson
2021-05-01 18:43 ` [PULL 25/31] Hexagon (target/hexagon) add A6_vminub_RdP Richard Henderson
2021-05-01 18:43 ` [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Richard Henderson
2021-05-01 18:43 ` [PULL 27/31] Hexagon (target/hexagon) circular addressing Richard Henderson
2021-05-01 18:43 ` [PULL 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing Richard Henderson
2021-05-01 18:43 ` [PULL 29/31] Hexagon (target/hexagon) load and unpack bytes instructions Richard Henderson
2021-05-01 18:43 ` [PULL 30/31] Hexagon (target/hexagon) load into shifted register instructions Richard Henderson
2021-05-01 18:43 ` [PULL 31/31] Hexagon (target/hexagon) CABAC decode bin Richard Henderson
2021-05-01 20:40 ` [PULL 00/31] target/hexagon patch queue Peter Maydell
2021-05-01 22:31 ` Richard Henderson
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