From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Taylor Simpson <tsimpson@quicinc.com>
Subject: [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics
Date: Sat, 1 May 2021 11:43:11 -0700 [thread overview]
Message-ID: <20210501184324.1338186-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210501184324.1338186-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
Change (cond ? (res = x) : (res = y)) to res = (cond ? x : y)
This makes the semnatics easier to for idef-parser to deal with
The following instructions are impacted
C2_any8
C2_all8
C2_mux
C2_muxii
C2_muxir
C2_muxri
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-14-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/imported/compare.idef | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/imported/compare.idef b/target/hexagon/imported/compare.idef
index 3551467854..abd016ffb5 100644
--- a/target/hexagon/imported/compare.idef
+++ b/target/hexagon/imported/compare.idef
@@ -198,11 +198,11 @@ Q6INSN(C4_or_orn,"Pd4=or(Ps4,or(Pt4,!Pu4))",ATTRIBS(A_CRSLOT23),
Q6INSN(C2_any8,"Pd4=any8(Ps4)",ATTRIBS(A_CRSLOT23),
"Logical ANY of low 8 predicate bits",
-{ PsV ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV ? 0xff : 0x00); })
Q6INSN(C2_all8,"Pd4=all8(Ps4)",ATTRIBS(A_CRSLOT23),
"Logical ALL of low 8 predicate bits",
-{ (PsV==0xff) ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV == 0xff ? 0xff : 0x00); })
Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
"Pack the odd and even bits of two predicate registers",
@@ -212,7 +212,7 @@ Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
Q6INSN(C2_mux,"Rd32=mux(Pu4,Rs32,Rt32)",ATTRIBS(),
"Scalar MUX",
-{ (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=RtV); })
+{ RdV = (fLSBOLD(PuV) ? RsV : RtV); })
Q6INSN(C2_cmovenewit,"if (Pu4.new) Rd32=#s12",ATTRIBS(A_ARCHV2),
@@ -269,18 +269,18 @@ Q6INSN(C2_ccombinewf,"if (!Pu4) Rdd32=combine(Rs32,Rt32)",ATTRIBS(A_ARCHV2),
Q6INSN(C2_muxii,"Rd32=mux(Pu4,#s8,#S8)",ATTRIBS(A_ARCHV2),
"Scalar MUX immediates",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=SiV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : SiV); })
Q6INSN(C2_muxir,"Rd32=mux(Pu4,Rs32,#s8)",ATTRIBS(A_ARCHV2),
"Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=siV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? RsV : siV); })
Q6INSN(C2_muxri,"Rd32=mux(Pu4,#s8,Rs32)",ATTRIBS(A_ARCHV2),
"Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=RsV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : RsV); })
--
2.25.1
next prev parent reply other threads:[~2021-05-01 19:04 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-01 18:42 [PULL 00/31] target/hexagon patch queue Richard Henderson
2021-05-01 18:42 ` [PULL 01/31] target/hexagon: translation changes Richard Henderson
2021-05-01 18:42 ` [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots Richard Henderson
2021-05-01 18:42 ` [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM Richard Henderson
2021-05-01 18:42 ` [PULL 04/31] target/hexagon: fix typo in comment Richard Henderson
2021-05-01 18:42 ` [PULL 05/31] target/hexagon: remove unnecessary semicolons Richard Henderson
2021-05-01 18:42 ` [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup Richard Henderson
2021-05-01 18:43 ` [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Richard Henderson
2021-05-01 18:43 ` [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives Richard Henderson
2021-05-01 18:43 ` [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu Richard Henderson
2021-05-01 18:43 ` [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Richard Henderson
2021-05-01 18:43 ` [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Richard Henderson
2021-05-01 18:43 ` [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate Richard Henderson
2021-05-01 18:43 ` [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function Richard Henderson
2021-05-01 18:43 ` [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes Richard Henderson
2021-05-01 18:43 ` [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess Richard Henderson
2021-05-01 18:43 ` [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Richard Henderson
2021-05-01 18:43 ` [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions Richard Henderson
2021-05-01 18:43 ` Richard Henderson [this message]
2021-05-01 18:43 ` [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition Richard Henderson
2021-05-01 18:43 ` [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Richard Henderson
2021-05-01 18:43 ` [PULL 21/31] Hexagon (target/hexagon) compile all debug code Richard Henderson
2021-05-01 18:43 ` [PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction Richard Henderson
2021-05-01 18:43 ` [PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta Richard Henderson
2021-05-01 18:43 ` [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh) Richard Henderson
2021-05-01 18:43 ` [PULL 25/31] Hexagon (target/hexagon) add A6_vminub_RdP Richard Henderson
2021-05-01 18:43 ` [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Richard Henderson
2021-05-01 18:43 ` [PULL 27/31] Hexagon (target/hexagon) circular addressing Richard Henderson
2021-05-01 18:43 ` [PULL 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing Richard Henderson
2021-05-01 18:43 ` [PULL 29/31] Hexagon (target/hexagon) load and unpack bytes instructions Richard Henderson
2021-05-01 18:43 ` [PULL 30/31] Hexagon (target/hexagon) load into shifted register instructions Richard Henderson
2021-05-01 18:43 ` [PULL 31/31] Hexagon (target/hexagon) CABAC decode bin Richard Henderson
2021-05-01 20:40 ` [PULL 00/31] target/hexagon patch queue Peter Maydell
2021-05-01 22:31 ` Richard Henderson
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