From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Taylor Simpson <tsimpson@quicinc.com>
Subject: [PULL 26/31] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
Date: Sat, 1 May 2021 11:43:19 -0700 [thread overview]
Message-ID: <20210501184324.1338186-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210501184324.1338186-1-richard.henderson@linaro.org>
From: Taylor Simpson <tsimpson@quicinc.com>
Rdd32 = add(Rss32, Rtt32, Px4):carry
Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
Sub with carry
Test cases in tests/tcg/hexagon/multi_result.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/gen_tcg.h | 37 ++++++++++++
target/hexagon/genptr.c | 11 ++++
tests/tcg/hexagon/multi_result.c | 82 +++++++++++++++++++++++++++
target/hexagon/imported/alu.idef | 15 +++++
target/hexagon/imported/encode_pp.def | 2 +
5 files changed, 147 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index aea0c55564..6bc578dfda 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -237,6 +237,43 @@
tcg_temp_free_i64(tmp); \
} while (0)
+/*
+ * Add or subtract with carry.
+ * Predicate register is used as an extra input and output.
+ * r5:4 = add(r1:0, r3:2, p1):carry
+ */
+#define fGEN_TCG_A4_addp_c(SHORTCODE) \
+ do { \
+ TCGv_i64 carry = tcg_temp_new_i64(); \
+ TCGv_i64 zero = tcg_const_i64(0); \
+ tcg_gen_extu_i32_i64(carry, PxV); \
+ tcg_gen_andi_i64(carry, carry, 1); \
+ tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
+ tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
+ tcg_gen_extrl_i64_i32(PxV, carry); \
+ gen_8bitsof(PxV, PxV); \
+ tcg_temp_free_i64(carry); \
+ tcg_temp_free_i64(zero); \
+ } while (0)
+
+/* r5:4 = sub(r1:0, r3:2, p1):carry */
+#define fGEN_TCG_A4_subp_c(SHORTCODE) \
+ do { \
+ TCGv_i64 carry = tcg_temp_new_i64(); \
+ TCGv_i64 zero = tcg_const_i64(0); \
+ TCGv_i64 not_RttV = tcg_temp_new_i64(); \
+ tcg_gen_extu_i32_i64(carry, PxV); \
+ tcg_gen_andi_i64(carry, carry, 1); \
+ tcg_gen_not_i64(not_RttV, RttV); \
+ tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
+ tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
+ tcg_gen_extrl_i64_i32(PxV, carry); \
+ gen_8bitsof(PxV, PxV); \
+ tcg_temp_free_i64(carry); \
+ tcg_temp_free_i64(zero); \
+ tcg_temp_free_i64(not_RttV); \
+ } while (0)
+
/*
* Compare each of the 8 unsigned bytes
* The minimum is placed in each byte of the destination.
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 9dbebc64b5..333f7d74bf 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -361,5 +361,16 @@ static inline void gen_store_conditional8(CPUHexagonState *env,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
+static TCGv gen_8bitsof(TCGv result, TCGv value)
+{
+ TCGv zero = tcg_const_tl(0);
+ TCGv ones = tcg_const_tl(0xff);
+ tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
+ tcg_temp_free(zero);
+ tcg_temp_free(ones);
+
+ return result;
+}
+
#include "tcg_funcs_generated.c.inc"
#include "tcg_func_table_generated.c.inc"
diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_result.c
index 95d99a0c90..52997b3128 100644
--- a/tests/tcg/hexagon/multi_result.c
+++ b/tests/tcg/hexagon/multi_result.c
@@ -85,6 +85,38 @@ static long long vminub(long long Rtt, long long Rss,
return result;
}
+static long long add_carry(long long Rss, long long Rtt,
+ int pred_in, int *pred_result)
+{
+ long long result;
+ int predval = pred_in;
+
+ asm volatile("p0 = %1\n\t"
+ "%0 = add(%2, %3, p0):carry\n\t"
+ "%1 = p0\n\t"
+ : "=r"(result), "+r"(predval)
+ : "r"(Rss), "r"(Rtt)
+ : "p0");
+ *pred_result = predval;
+ return result;
+}
+
+static long long sub_carry(long long Rss, long long Rtt,
+ int pred_in, int *pred_result)
+{
+ long long result;
+ int predval = pred_in;
+
+ asm volatile("p0 = !cmp.eq(%1, #0)\n\t"
+ "%0 = sub(%2, %3, p0):carry\n\t"
+ "%1 = p0\n\t"
+ : "=r"(result), "+r"(predval)
+ : "r"(Rss), "r"(Rtt)
+ : "p0");
+ *pred_result = predval;
+ return result;
+}
+
int err;
static void check_ll(long long val, long long expect)
@@ -188,12 +220,62 @@ static void test_vminub()
check_p(pred_result, 0xaa);
}
+static void test_add_carry()
+{
+ long long res64;
+ int pred_result;
+
+ res64 = add_carry(0x0000000000000000LL,
+ 0xffffffffffffffffLL,
+ 1, &pred_result);
+ check_ll(res64, 0x0000000000000000LL);
+ check_p(pred_result, 0xff);
+
+ res64 = add_carry(0x0000000100000000LL,
+ 0xffffffffffffffffLL,
+ 0, &pred_result);
+ check_ll(res64, 0x00000000ffffffffLL);
+ check_p(pred_result, 0xff);
+
+ res64 = add_carry(0x0000000100000000LL,
+ 0xffffffffffffffffLL,
+ 0, &pred_result);
+ check_ll(res64, 0x00000000ffffffffLL);
+ check_p(pred_result, 0xff);
+}
+
+static void test_sub_carry()
+{
+ long long res64;
+ int pred_result;
+
+ res64 = sub_carry(0x0000000000000000LL,
+ 0x0000000000000000LL,
+ 1, &pred_result);
+ check_ll(res64, 0x0000000000000000LL);
+ check_p(pred_result, 0xff);
+
+ res64 = sub_carry(0x0000000100000000LL,
+ 0x0000000000000000LL,
+ 0, &pred_result);
+ check_ll(res64, 0x00000000ffffffffLL);
+ check_p(pred_result, 0xff);
+
+ res64 = sub_carry(0x0000000100000000LL,
+ 0x0000000000000000LL,
+ 0, &pred_result);
+ check_ll(res64, 0x00000000ffffffffLL);
+ check_p(pred_result, 0xff);
+}
+
int main()
{
test_sfrecipa();
test_sfinvsqrta();
test_vacsh();
test_vminub();
+ test_add_carry();
+ test_sub_carry();
puts(err ? "FAIL" : "PASS");
return err;
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index f0c9bb47ec..58477ae40a 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -153,6 +153,21 @@ Q6INSN(A2_subp,"Rdd32=sub(Rtt32,Rss32)",ATTRIBS(),
"Sub",
{ RddV=RttV-RssV;})
+/* 64-bit with carry */
+
+Q6INSN(A4_addp_c,"Rdd32=add(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Add with Carry",
+{
+ RddV = RssV + RttV + fLSBOLD(PxV);
+ PxV = f8BITSOF(fCARRY_FROM_ADD(RssV,RttV,fLSBOLD(PxV)));
+})
+
+Q6INSN(A4_subp_c,"Rdd32=sub(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Sub with Carry",
+{
+ RddV = RssV + ~RttV + fLSBOLD(PxV);
+ PxV = f8BITSOF(fCARRY_FROM_ADD(RssV,~RttV,fLSBOLD(PxV)));
+})
+
+
/* NEG and ABS */
Q6INSN(A2_negsat,"Rd32=neg(Rs32):sat",ATTRIBS(),
diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def
index 46193984c5..514c2404ce 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -1749,6 +1749,8 @@ SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-","ddddd")
DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rdd=(Rss,Rtt,Pu)")
SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd")
SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd")
+SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd")
+SH_RRR_ENC(A4_subp_c, "0010","111","-","-xx","ddddd")
DEF_FIELDROW_DESC32(ICLASS_S3op" 0011 -------- PP------ --------","[#3] Rdd=(Rss,Rt)")
--
2.25.1
next prev parent reply other threads:[~2021-05-01 19:13 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-01 18:42 [PULL 00/31] target/hexagon patch queue Richard Henderson
2021-05-01 18:42 ` [PULL 01/31] target/hexagon: translation changes Richard Henderson
2021-05-01 18:42 ` [PULL 02/31] target/hexagon: remove unnecessary checks in find_iclass_slots Richard Henderson
2021-05-01 18:42 ` [PULL 03/31] target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM Richard Henderson
2021-05-01 18:42 ` [PULL 04/31] target/hexagon: fix typo in comment Richard Henderson
2021-05-01 18:42 ` [PULL 05/31] target/hexagon: remove unnecessary semicolons Richard Henderson
2021-05-01 18:42 ` [PULL 06/31] Hexagon (target/hexagon) TCG generation cleanup Richard Henderson
2021-05-01 18:43 ` [PULL 07/31] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Richard Henderson
2021-05-01 18:43 ` [PULL 08/31] Hexagon (target/hexagon) remove unnecessary inline directives Richard Henderson
2021-05-01 18:43 ` [PULL 09/31] Hexagon (target/hexagon) use env_archcpu and env_cpu Richard Henderson
2021-05-01 18:43 ` [PULL 10/31] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Richard Henderson
2021-05-01 18:43 ` [PULL 11/31] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Richard Henderson
2021-05-01 18:43 ` [PULL 12/31] Hexagon (target/hexagon) change variables from int to bool when appropriate Richard Henderson
2021-05-01 18:43 ` [PULL 13/31] Hexagon (target/hexagon) remove unused carry_from_add64 function Richard Henderson
2021-05-01 18:43 ` [PULL 14/31] Hexagon (target/hexagon) change type of softfloat_roundingmodes Richard Henderson
2021-05-01 18:43 ` [PULL 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess Richard Henderson
2021-05-01 18:43 ` [PULL 16/31] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Richard Henderson
2021-05-01 18:43 ` [PULL 17/31] Hexagon (target/hexagon) use softfloat for float-to-int conversions Richard Henderson
2021-05-01 18:43 ` [PULL 18/31] Hexagon (target/hexagon) cleanup ternary operators in semantics Richard Henderson
2021-05-01 18:43 ` [PULL 19/31] Hexagon (target/hexagon) cleanup reg_field_info definition Richard Henderson
2021-05-01 18:43 ` [PULL 20/31] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Richard Henderson
2021-05-01 18:43 ` [PULL 21/31] Hexagon (target/hexagon) compile all debug code Richard Henderson
2021-05-01 18:43 ` [PULL 22/31] Hexagon (target/hexagon) add F2_sfrecipa instruction Richard Henderson
2021-05-01 18:43 ` [PULL 23/31] Hexagon (target/hexagon) add F2_sfinvsqrta Richard Henderson
2021-05-01 18:43 ` [PULL 24/31] Hexagon (target/hexagon) add A5_ACS (vacsh) Richard Henderson
2021-05-01 18:43 ` [PULL 25/31] Hexagon (target/hexagon) add A6_vminub_RdP Richard Henderson
2021-05-01 18:43 ` Richard Henderson [this message]
2021-05-01 18:43 ` [PULL 27/31] Hexagon (target/hexagon) circular addressing Richard Henderson
2021-05-01 18:43 ` [PULL 28/31] Hexagon (target/hexagon) bit reverse (brev) addressing Richard Henderson
2021-05-01 18:43 ` [PULL 29/31] Hexagon (target/hexagon) load and unpack bytes instructions Richard Henderson
2021-05-01 18:43 ` [PULL 30/31] Hexagon (target/hexagon) load into shifted register instructions Richard Henderson
2021-05-01 18:43 ` [PULL 31/31] Hexagon (target/hexagon) CABAC decode bin Richard Henderson
2021-05-01 20:40 ` [PULL 00/31] target/hexagon patch queue Peter Maydell
2021-05-01 22:31 ` Richard Henderson
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