From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PULL 04/36] target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode
Date: Sun, 2 May 2021 18:15:06 +0200 [thread overview]
Message-ID: <20210502161538.534038-5-f4bug@amsat.org> (raw)
In-Reply-To: <20210502161538.534038-1-f4bug@amsat.org>
When running with '-d unimp' all MTHC0 opcode executed
are logged as unimplemented... Add the proper 'return'
statement missed from commit 5204ea79ea7.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210422081055.2349216-1-f4bug@amsat.org>
---
target/mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8a0a2197426..3230b2bca3b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5945,6 +5945,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
trace_mips_translate_c0("mthc0", register_name, reg, sel);
+ return;
cp0_unimplemented:
qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
--
2.26.3
next prev parent reply other threads:[~2021-05-02 16:31 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-02 16:15 [PULL 00/36] MIPS patches for 2021-05-02 Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing) Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes Philippe Mathieu-Daudé
2021-05-02 16:15 ` Philippe Mathieu-Daudé [this message]
2021-05-02 16:15 ` [PULL 05/36] target/mips: Migrate missing CPU fields Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 07/36] target/mips: Simplify meson TCG rules Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 09/36] target/mips: Move msa_reset() " Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 13/36] target/mips: Turn printfpr() macro into a proper function Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 14/36] target/mips: Declare mips_env_set_pc() inlined in "internal.h" Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 16/36] target/mips: Extract load/store helpers to ldst_helper.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 17/36] meson: Introduce meson_user_arch source set for arch-specific user-mode Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 18/36] target/mips: Introduce tcg-internal.h for TCG specific declarations Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 19/36] target/mips: Add simple user-mode mips_cpu_do_interrupt() Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 20/36] target/mips: Add simple user-mode mips_cpu_tlb_fill() Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 21/36] target/mips: Move cpu_signal_handler definition around Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 22/36] target/mips: Move sysemu specific files under sysemu/ subfolder Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 23/36] target/mips: Move physical addressing code to sysemu/physaddr.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 24/36] target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 25/36] target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 26/36] target/mips: Restrict mmu_init() to TCG Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 27/36] target/mips: Move tlb_helper.c to tcg/sysemu/ Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 28/36] target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 29/36] target/mips: Move Special opcodes to tcg/sysemu/special_helper.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 30/36] target/mips: Move helper_cache() " Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 31/36] target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 32/36] target/mips: Move exception management code to exception.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 33/36] target/mips: Move CP0 helpers to sysemu/cp0.c Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 34/36] target/mips: Move TCG source files under tcg/ sub directory Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 35/36] hw/mips: Restrict non-virtualized machines to TCG Philippe Mathieu-Daudé
2021-05-02 16:15 ` [PULL 36/36] gitlab-ci: Add KVM mips64el cross-build jobs Philippe Mathieu-Daudé
2021-05-02 16:24 ` [PULL 00/36] MIPS patches for 2021-05-02 no-reply
2021-05-04 9:09 ` Peter Maydell
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