From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 03/46] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags
Date: Tue, 4 May 2021 15:52:29 +1000 [thread overview]
Message-ID: <20210504055312.306823-4-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au>
From: Richard Henderson <richard.henderson@linaro.org>
Keep all hflags computation in one place, as this will be
especially important later.
Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when
LE should be taken from HID0. This appears to be set if
and only if POWERPC_FLAG_RTC_CLK is set, but we're not
short of bits and having both names will avoid confusion.
Note that this was the only user of hflags_nmsr, so we can
perform a straight assignment rather than mask and set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-3-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper_regs.c | 13 +++++++++++--
target/ppc/misc_helper.c | 8 +++-----
target/ppc/translate_init.c.inc | 4 ++--
4 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68..061d2eed1b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -581,6 +581,8 @@ enum {
POWERPC_FLAG_TM = 0x00100000,
/* Has SCV (ISA 3.00) */
POWERPC_FLAG_SCV = 0x00200000,
+ /* Has HID0 for LE bit (601) */
+ POWERPC_FLAG_HID0_LE = 0x00400000,
};
/*****************************************************************************/
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 5e18232b84..95b9aca61f 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -96,8 +96,17 @@ void hreg_compute_hflags(CPUPPCState *env)
hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
- /* Merge with hflags coming from other registers */
- env->hflags |= env->hflags_nmsr;
+
+ if (env->flags & POWERPC_FLAG_HID0_LE) {
+ /*
+ * Note that MSR_LE is not set in env->msr_mask for this cpu,
+ * and so will never be set in msr or hflags at this point.
+ */
+ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1);
+ env->hflags |= le << MSR_LE;
+ /* Retain for backward compatibility with migration. */
+ env->hflags_nmsr = le << MSR_LE;
+ }
}
void cpu_interrupt_exittb(CPUState *cs)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 5d6e0de396..63e3147eb4 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -194,16 +194,14 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
target_ulong hid0;
hid0 = env->spr[SPR_HID0];
+ env->spr[SPR_HID0] = (uint32_t)val;
+
if ((val ^ hid0) & 0x00000008) {
/* Change current endianness */
- env->hflags &= ~(1 << MSR_LE);
- env->hflags_nmsr &= ~(1 << MSR_LE);
- env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
- env->hflags |= env->hflags_nmsr;
+ hreg_compute_hflags(env);
qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
val & 0x8 ? 'l' : 'b', env->hflags);
}
- env->spr[SPR_HID0] = (uint32_t)val;
}
void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index c03a7c4f52..049d76cfd1 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -5441,7 +5441,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
pcc->excp_model = POWERPC_EXCP_601;
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_601;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
}
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
@@ -5485,7 +5485,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
#endif
pcc->bus_model = PPC_FLAGS_INPUT_6xx;
pcc->bfd_mach = bfd_mach_ppc_601;
- pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
+ pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
}
static void init_proc_602(CPUPPCState *env)
--
2.31.1
next prev parent reply other threads:[~2021-05-04 5:56 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 5:52 [PULL 00/46] ppc-for-6.1 queue 20210504 David Gibson
2021-05-04 5:52 ` [PULL 01/46] hw/ppc/mac_newworld: Restrict RAM to 2 GiB David Gibson
2021-05-04 5:52 ` [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line David Gibson
2021-05-04 5:52 ` David Gibson [this message]
2021-05-04 5:52 ` [PULL 04/46] target/ppc: Properly sync cpu state with new msr in cpu_load_old David Gibson
2021-05-04 5:52 ` [PULL 05/46] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr David Gibson
2021-05-04 5:52 ` [PULL 06/46] target/ppc: Retain hflags_nmsr only for migration David Gibson
2021-05-04 5:52 ` [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1} David Gibson
2021-05-04 5:52 ` [PULL 08/46] hw/ppc/pnv_core: Update hflags after setting msr David Gibson
2021-05-04 5:52 ` [PULL 09/46] hw/ppc/spapr_rtas: " David Gibson
2021-05-04 5:52 ` [PULL 10/46] target/ppc: Extract post_load_update_msr David Gibson
2021-05-04 5:52 ` [PULL 11/46] target/ppc: Disconnect hflags from MSR David Gibson
2021-05-04 5:52 ` [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t David Gibson
2021-05-04 5:52 ` [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags David Gibson
2021-05-04 5:52 ` [PULL 14/46] target/ppc: Create helper_scv David Gibson
2021-05-04 5:52 ` [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags David Gibson
2021-05-04 5:52 ` [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags David Gibson
2021-05-04 5:52 ` [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx David Gibson
2021-05-04 5:52 ` [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling David Gibson
2021-05-04 5:52 ` [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG David Gibson
2021-05-04 5:52 ` [PULL 20/46] vt82c686: QOM-ify superio related functionality David Gibson
2021-05-04 5:52 ` [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO David Gibson
2021-05-04 5:52 ` [PULL 22/46] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it David Gibson
2021-05-04 5:52 ` [PULL 23/46] vt82c686: Add emulation of VT8231 south bridge David Gibson
2021-05-04 5:52 ` [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller David Gibson
2021-05-04 5:52 ` [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II David Gibson
2021-05-04 5:52 ` [PULL 26/46] spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR David Gibson
2021-05-04 5:52 ` [PULL 27/46] ppc/spapr: Add support for implement support for H_SCM_HEALTH David Gibson
2021-05-04 5:52 ` [PULL 28/46] roms/Makefile: Update ppce500 u-boot build directory name David Gibson
2021-05-04 5:52 ` [PULL 29/46] roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support David Gibson
2021-05-04 5:52 ` [PULL 30/46] docs/system: ppc: Add documentation for ppce500 machine David Gibson
2021-05-04 5:52 ` [PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour David Gibson
2021-05-04 5:52 ` [PULL 32/46] target/ppc: POWER10 supports scv David Gibson
2021-05-04 5:52 ` [PULL 33/46] ppc: Rename current DAWR macros and variables David Gibson
2021-05-04 5:53 ` [PULL 34/46] spapr.c: do not use MachineClass::max_cpus to limit CPUs David Gibson
2021-05-04 5:53 ` [PULL 35/46] spapr.h: increase FDT_MAX_SIZE David Gibson
2021-05-04 5:53 ` [PULL 36/46] spapr_drc.c: handle hotunplug errors in drc_unisolate_logical() David Gibson
2021-05-04 5:53 ` [PULL 37/46] target/ppc: code motion from translate_init.c.inc to gdbstub.c David Gibson
2021-05-04 5:53 ` [PULL 38/46] target/ppc: move opcode table logic to translate.c David Gibson
2021-05-04 5:53 ` [PULL 39/46] target/ppc: rework AIL logic in interrupt delivery David Gibson
2021-05-04 5:53 ` [PULL 40/46] target/ppc: Add POWER10 exception model David Gibson
2021-05-04 5:53 ` [PULL 41/46] target/ppc: Clean up _spr_register et al David Gibson
2021-05-04 5:53 ` [PULL 42/46] target/ppc: Reduce the size of ppc_spr_t David Gibson
2021-05-04 5:53 ` [PULL 43/46] target/ppc: removed VSCR from SPR registration David Gibson
2021-05-04 5:53 ` [PULL 44/46] hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset() David Gibson
2021-05-04 5:53 ` [PULL 45/46] hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset() David Gibson
2021-05-04 5:53 ` [PULL 46/46] hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset() David Gibson
2021-05-06 17:54 ` [PULL 00/46] ppc-for-6.1 queue 20210504 Peter Maydell
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