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From: "Lukas Jünger" <lukas.juenger@greensocs.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com,
	mark.burton@greensocs.com, marcandre.lureau@redhat.com,
	palmer@dabbelt.com, pbonzini@redhat.com,
	alistair.francis@wdc.com,
	"Lukas Jünger" <lukas.juenger@greensocs.com>,
	luc.michel@greensocs.com
Subject: [PATCH 1/2] Consistent function names for sifive uart read and write function
Date: Tue,  4 May 2021 17:34:55 +0200	[thread overview]
Message-ID: <20210504153456.927083-2-lukas.juenger@greensocs.com> (raw)
In-Reply-To: <20210504153456.927083-1-lukas.juenger@greensocs.com>

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 hw/char/sifive_uart.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 3a00ba7f00..cb70374ead 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
 }
 
 static uint64_t
-uart_read(void *opaque, hwaddr addr, unsigned int size)
+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     unsigned char r;
@@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
 }
 
 static void
-uart_write(void *opaque, hwaddr addr,
-           uint64_t val64, unsigned int size)
+sifive_uart_write(void *opaque, hwaddr addr,
+                  uint64_t val64, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     uint32_t value = val64;
@@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
                   __func__, (int)addr, (int)value);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
+static const MemoryRegionOps sifive_uart_ops = {
+    .read = sifive_uart_read,
+    .write = sifive_uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 4,
@@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
         uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
+    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
                           TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
     memory_region_add_subregion(address_space, base, &s->mmio);
     return s;
-- 
2.30.2



  reply	other threads:[~2021-05-04 16:54 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-04 15:34 [PATCH 0/2] QOMify Sifive UART model Lukas Jünger
2021-05-04 15:34 ` Lukas Jünger [this message]
2021-05-06  2:12   ` [PATCH 1/2] Consistent function names for sifive uart read and write function Alistair Francis
2021-05-11 11:38   ` Luc Michel
2021-05-11 13:06   ` Bin Meng
2021-05-04 15:34 ` [PATCH 2/2] QOMify sifive_uart model Lukas Jünger
2021-05-11 11:39   ` Luc Michel
2021-05-11 12:26   ` Philippe Mathieu-Daudé
2021-05-16 11:13     ` Lukas Jünger

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