From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Claudio Fontana <cfontana@suse.de>
Subject: [PULL 17/33] target/i386: gdbstub: introduce aux functions to read/write CS64 regs
Date: Tue, 11 May 2021 04:13:34 -0400 [thread overview]
Message-ID: <20210511081350.419428-18-pbonzini@redhat.com> (raw)
In-Reply-To: <20210511081350.419428-1-pbonzini@redhat.com>
From: Claudio Fontana <cfontana@suse.de>
a number of registers are read as 64bit under the condition that
(hflags & HF_CS64_MASK) || TARGET_X86_64)
and a number of registers are written as 64bit under the condition that
(hflags & HF_CS64_MASK).
Provide some auxiliary functions that do that.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210322132800.7470-20-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/gdbstub.c | 155 ++++++++++++++----------------------------
1 file changed, 51 insertions(+), 104 deletions(-)
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 41e265fc67..4ad1295425 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -78,6 +78,23 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define GDB_FORCE_64 0
#endif
+static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val)
+{
+ if ((hflags & HF_CS64_MASK) || GDB_FORCE_64) {
+ return gdb_get_reg64(buf, val);
+ }
+ return gdb_get_reg32(buf, val);
+}
+
+static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)
+{
+ if (hflags & HF_CS64_MASK) {
+ *val = ldq_p(buf);
+ return 8;
+ }
+ *val = ldl_p(buf);
+ return 4;
+}
int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
@@ -142,25 +159,14 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
case IDX_SEG_REGS + 5:
return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
-
case IDX_SEG_REGS + 6:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->segs[R_FS].base);
- }
- return gdb_get_reg32(mem_buf, env->segs[R_FS].base);
-
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base);
case IDX_SEG_REGS + 7:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->segs[R_GS].base);
- }
- return gdb_get_reg32(mem_buf, env->segs[R_GS].base);
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base);
case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->kernelgsbase);
- }
- return gdb_get_reg32(mem_buf, env->kernelgsbase);
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase);
#else
return gdb_get_reg32(mem_buf, 0);
#endif
@@ -188,45 +194,23 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_reg32(mem_buf, env->mxcsr);
case IDX_CTL_CR0_REG:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->cr[0]);
- }
- return gdb_get_reg32(mem_buf, env->cr[0]);
-
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]);
case IDX_CTL_CR2_REG:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->cr[2]);
- }
- return gdb_get_reg32(mem_buf, env->cr[2]);
-
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]);
case IDX_CTL_CR3_REG:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->cr[3]);
- }
- return gdb_get_reg32(mem_buf, env->cr[3]);
-
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]);
case IDX_CTL_CR4_REG:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->cr[4]);
- }
- return gdb_get_reg32(mem_buf, env->cr[4]);
-
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]);
case IDX_CTL_CR8_REG:
-#ifdef CONFIG_SOFTMMU
+#ifndef CONFIG_USER_ONLY
tpr = cpu_get_apic_tpr(cpu->apic_state);
#else
tpr = 0;
#endif
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, tpr);
- }
- return gdb_get_reg32(mem_buf, tpr);
+ return gdb_read_reg_cs64(env->hflags, mem_buf, tpr);
case IDX_CTL_EFER_REG:
- if ((env->hflags & HF_CS64_MASK) || GDB_FORCE_64) {
- return gdb_get_reg64(mem_buf, env->efer);
- }
- return gdb_get_reg32(mem_buf, env->efer);
+ return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer);
}
}
return 0;
@@ -266,7 +250,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- uint32_t tmp;
+ target_ulong tmp;
+ int len;
/* N.B. GDB can't deal with changes in registers or sizes in the middle
of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
@@ -329,30 +314,13 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
case IDX_SEG_REGS + 5:
return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
-
case IDX_SEG_REGS + 6:
- if (env->hflags & HF_CS64_MASK) {
- env->segs[R_FS].base = ldq_p(mem_buf);
- return 8;
- }
- env->segs[R_FS].base = ldl_p(mem_buf);
- return 4;
-
+ return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base);
case IDX_SEG_REGS + 7:
- if (env->hflags & HF_CS64_MASK) {
- env->segs[R_GS].base = ldq_p(mem_buf);
- return 8;
- }
- env->segs[R_GS].base = ldl_p(mem_buf);
- return 4;
-
+ return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base);
case IDX_SEG_REGS + 8:
#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- env->kernelgsbase = ldq_p(mem_buf);
- return 8;
- }
- env->kernelgsbase = ldl_p(mem_buf);
+ return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase);
#endif
return 4;
@@ -382,57 +350,36 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return 4;
case IDX_CTL_CR0_REG:
- if (env->hflags & HF_CS64_MASK) {
- cpu_x86_update_cr0(env, ldq_p(mem_buf));
- return 8;
- }
- cpu_x86_update_cr0(env, ldl_p(mem_buf));
- return 4;
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+ cpu_x86_update_cr0(env, tmp);
+ return len;
case IDX_CTL_CR2_REG:
- if (env->hflags & HF_CS64_MASK) {
- env->cr[2] = ldq_p(mem_buf);
- return 8;
- }
- env->cr[2] = ldl_p(mem_buf);
- return 4;
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+ env->cr[2] = tmp;
+ return len;
case IDX_CTL_CR3_REG:
- if (env->hflags & HF_CS64_MASK) {
- cpu_x86_update_cr3(env, ldq_p(mem_buf));
- return 8;
- }
- cpu_x86_update_cr3(env, ldl_p(mem_buf));
- return 4;
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+ cpu_x86_update_cr3(env, tmp);
+ return len;
case IDX_CTL_CR4_REG:
- if (env->hflags & HF_CS64_MASK) {
- cpu_x86_update_cr4(env, ldq_p(mem_buf));
- return 8;
- }
- cpu_x86_update_cr4(env, ldl_p(mem_buf));
- return 4;
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+ cpu_x86_update_cr4(env, tmp);
+ return len;
case IDX_CTL_CR8_REG:
- if (env->hflags & HF_CS64_MASK) {
-#ifdef CONFIG_SOFTMMU
- cpu_set_apic_tpr(cpu->apic_state, ldq_p(mem_buf));
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+#ifndef CONFIG_USER_ONLY
+ cpu_set_apic_tpr(cpu->apic_state, tmp);
#endif
- return 8;
- }
-#ifdef CONFIG_SOFTMMU
- cpu_set_apic_tpr(cpu->apic_state, ldl_p(mem_buf));
-#endif
- return 4;
+ return len;
case IDX_CTL_EFER_REG:
- if (env->hflags & HF_CS64_MASK) {
- cpu_load_efer(env, ldq_p(mem_buf));
- return 8;
- }
- cpu_load_efer(env, ldl_p(mem_buf));
- return 4;
-
+ len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp);
+ cpu_load_efer(env, tmp);
+ return len;
}
}
/* Unrecognised register. */
--
2.26.2
next prev parent reply other threads:[~2021-05-11 8:24 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 8:13 [PULL 00/33] Misc (mostly i386) patches for 2021-05-11 Paolo Bonzini
2021-05-11 8:13 ` [PULL 01/33] target/i386: Rename helper_fldt, helper_fstt Paolo Bonzini
2021-05-11 8:13 ` [PULL 02/33] target/i386: Split out do_fsave, do_frstor, do_fxsave, do_fxrstor Paolo Bonzini
2021-05-11 8:13 ` [PULL 03/33] i386: split cpu accelerators from cpu.c, using AccelCPUClass Paolo Bonzini
2021-08-20 16:55 ` Peter Maydell
2021-08-20 17:02 ` Philippe Mathieu-Daudé
2021-08-20 17:10 ` Peter Maydell
2021-05-11 8:13 ` [PULL 04/33] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Paolo Bonzini
2021-05-11 8:13 ` [PULL 05/33] accel: introduce new accessor functions Paolo Bonzini
2021-05-11 8:13 ` [PULL 06/33] target/i386: fix host_cpu_adjust_phys_bits error handling Paolo Bonzini
2021-05-11 8:13 ` [PULL 07/33] accel-cpu: make cpu_realizefn return a bool Paolo Bonzini
2021-05-11 8:13 ` [PULL 08/33] i386: split off sysemu-only functionality in tcg-cpu Paolo Bonzini
2021-05-11 8:13 ` [PULL 09/33] i386: split smm helper (sysemu) Paolo Bonzini
2021-05-11 8:13 ` [PULL 10/33] i386: split tcg excp_helper into sysemu and user parts Paolo Bonzini
2021-05-11 8:13 ` [PULL 11/33] i386: move TCG bpt_helper into sysemu/ Paolo Bonzini
2021-05-11 8:13 ` [PULL 12/33] i386: split misc helper user stubs and sysemu part Paolo Bonzini
2021-05-11 8:13 ` [PULL 13/33] i386: separate fpu_helper sysemu-only parts Paolo Bonzini
2021-05-11 8:13 ` [PULL 14/33] i386: split svm_helper into sysemu and stub-only user Paolo Bonzini
2021-05-11 8:13 ` [PULL 15/33] i386: split seg_helper into user-only and sysemu parts Paolo Bonzini
2021-05-11 8:13 ` [PULL 16/33] i386: split off sysemu part of cpu.c Paolo Bonzini
2021-05-11 8:13 ` Paolo Bonzini [this message]
2021-05-11 8:13 ` [PULL 18/33] target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu Paolo Bonzini
2021-05-11 8:13 ` [PULL 19/33] i386: make cpu_load_efer sysemu-only Paolo Bonzini
2021-05-11 8:13 ` [PULL 20/33] accel: move call to accel_init_interfaces Paolo Bonzini
2021-05-11 8:13 ` [PULL 21/33] accel: add init_accel_cpu for adapting accel behavior to CPU type Paolo Bonzini
2021-05-11 8:13 ` [PULL 22/33] target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants Paolo Bonzini
2021-05-11 8:13 ` [PULL 23/33] target/i386: move paging mode constants from SVM to cpu.h Paolo Bonzini
2021-05-11 8:13 ` [PULL 24/33] target/i386: extract mmu_translate Paolo Bonzini
2021-05-11 8:13 ` [PULL 25/33] target/i386: pass cr3 to mmu_translate Paolo Bonzini
2021-05-11 8:13 ` [PULL 26/33] target/i386: extend pg_mode to more CR0 and CR4 bits Paolo Bonzini
2021-05-11 8:13 ` [PULL 27/33] target/i386: allow customizing the next phase of the translation Paolo Bonzini
2021-05-11 8:13 ` [PULL 28/33] target/i386: use mmu_translate for NPT walk Paolo Bonzini
2021-05-11 8:13 ` [PULL 29/33] main-loop: remove dead code Paolo Bonzini
2021-05-11 8:13 ` [PULL 30/33] migration: do not restart VM after successful snapshot-load Paolo Bonzini
2021-05-11 8:56 ` Dr. David Alan Gilbert
2021-05-12 8:05 ` Paolo Bonzini
2021-05-11 9:09 ` Daniel P. Berrangé
2021-05-11 17:06 ` Daniel P. Berrangé
2021-05-12 7:45 ` Kevin Wolf
2021-05-12 18:11 ` Paolo Bonzini
2021-05-11 8:13 ` [PULL 31/33] qemu-option: support accept-any QemuOptsList in qemu_opts_absorb_qdict Paolo Bonzini
2021-05-11 8:13 ` [PULL 32/33] configure: fix detection of gdbus-codegen Paolo Bonzini
2021-05-11 8:13 ` [PULL 33/33] coverity-scan: list components, move model to scripts/coverity-scan Paolo Bonzini
2021-05-11 8:48 ` [PULL 00/33] Misc (mostly i386) patches for 2021-05-11 no-reply
2021-05-12 16:29 ` Peter Maydell
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