From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Anup Patel <anup@brainfault.org>
Subject: [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available
Date: Fri, 14 May 2021 20:02:42 +0530 [thread overview]
Message-ID: <20210514143242.377645-5-anup.patel@wdc.com> (raw)
In-Reply-To: <20210514143242.377645-1-anup.patel@wdc.com>
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/virt.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c0dc69ff33..981a3a06d5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -262,8 +262,15 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, intc_name);
intc_phandle = phandle++;
qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
- qemu_fdt_setprop_string(fdt, intc_name, "compatible",
- "riscv,cpu-intc");
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_AIA)) {
+ const char intcomp[] = "riscv,cpu-intc-aia\0riscv,cpu-intc";
+ qemu_fdt_setprop(fdt, name, "compatible",
+ intcomp, sizeof(intcomp));
+ } else {
+ qemu_fdt_setprop_string(fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ }
qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
--
2.25.1
next prev parent reply other threads:[~2021-05-14 14:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 14:32 [PATCH 0/4] AIA local interrupt CSR support Anup Patel
2021-05-14 14:32 ` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs Anup Patel
2021-06-10 22:26 ` Alistair Francis
2021-05-14 14:32 ` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs Anup Patel
2021-06-10 23:15 ` Alistair Francis
2021-06-11 4:58 ` Anup Patel
2021-05-14 14:32 ` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs Anup Patel
2021-06-10 23:19 ` Alistair Francis
2021-06-11 5:04 ` Anup Patel
2021-06-11 8:45 ` Alistair Francis
2021-06-11 14:04 ` Anup Patel
2021-06-15 8:11 ` Alistair Francis
2021-06-15 12:48 ` Anup Patel
2021-05-14 14:32 ` Anup Patel [this message]
2021-06-10 23:20 ` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2021-06-11 6:47 ` [PATCH 0/4] AIA local interrupt CSR support Anup Patel
2021-06-11 8:40 ` Alistair Francis
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