From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Cornelia Huck" <cohuck@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Halil Pasic" <pasic@linux.ibm.com>,
"Christian Borntraeger" <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v2 03/26] s390x/tcg: Simplify vop64_3() handling
Date: Mon, 17 May 2021 16:27:16 +0200 [thread overview]
Message-ID: <20210517142739.38597-4-david@redhat.com> (raw)
In-Reply-To: <20210517142739.38597-1-david@redhat.com>
Let's simplify, reworking our handler generation, passing the whole "m5"
register content and not providing specialized handlers for "se", and
reading/writing proper float64 values using new helpers.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 4 --
target/s390x/translate_vx.c.inc | 11 ++--
target/s390x/vec_fpu_helper.c | 94 +++++++++------------------------
3 files changed, 30 insertions(+), 79 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index d4e4f3388f..2344f81273 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -247,7 +247,6 @@ DEF_HELPER_6(gvec_vstrc_cc_rt32, void, ptr, cptr, cptr, cptr, env, i32)
/* === Vector Floating-Point Instructions */
DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfa64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
@@ -271,7 +270,6 @@ DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
@@ -279,7 +277,6 @@ DEF_HELPER_FLAGS_4(gvec_vfll32s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfm64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfma64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfma64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_vfms64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, env, i32)
@@ -287,7 +284,6 @@ DEF_HELPER_FLAGS_6(gvec_vfms64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, cptr, en
DEF_HELPER_FLAGS_4(gvec_vfsq64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfsq64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfs64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
-DEF_HELPER_FLAGS_5(gvec_vfs64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci64, void, ptr, cptr, env, i32)
DEF_HELPER_4(gvec_vftci64s, void, ptr, cptr, env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index eb767f5288..2d3fbdfab2 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2443,7 +2443,6 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
{
const uint8_t fpf = get_field(s, m4);
const uint8_t m5 = get_field(s, m5);
- const bool se = extract32(m5, 3, 1);
gen_helper_gvec_3_ptr *fn;
if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
@@ -2453,22 +2452,22 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
switch (s->fields.op2) {
case 0xe3:
- fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;
+ fn = gen_helper_gvec_vfa64;
break;
case 0xe5:
- fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;
+ fn = gen_helper_gvec_vfd64;
break;
case 0xe7:
- fn = se ? gen_helper_gvec_vfm64s : gen_helper_gvec_vfm64;
+ fn = gen_helper_gvec_vfm64;
break;
case 0xe2:
- fn = se ? gen_helper_gvec_vfs64s : gen_helper_gvec_vfs64;
+ fn = gen_helper_gvec_vfs64;
break;
default:
g_assert_not_reached();
}
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
- get_field(s, v3), cpu_env, 0, fn);
+ get_field(s, v3), cpu_env, m5, fn);
return DISAS_NEXT;
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index d485837930..f33ee6e774 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -78,6 +78,16 @@ static void handle_ieee_exc(CPUS390XState *env, uint8_t vxc, uint8_t vec_exc,
}
}
+static float64 s390_vec_read_float64(const S390Vector *v, uint8_t enr)
+{
+ return make_float64(s390_vec_read_element64(v, enr));
+}
+
+static void s390_vec_write_float64(S390Vector *v, uint8_t enr, float64 data)
+{
+ return s390_vec_write_element64(v, enr, data);
+}
+
typedef uint64_t (*vop64_2_fn)(uint64_t a, float_status *s);
static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
bool s, bool XxC, uint8_t erm, vop64_2_fn fn,
@@ -102,7 +112,7 @@ static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
*v1 = tmp;
}
-typedef uint64_t (*vop64_3_fn)(uint64_t a, uint64_t b, float_status *s);
+typedef float64 (*vop64_3_fn)(float64 a, float64 b, float_status *s);
static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
CPUS390XState *env, bool s, vop64_3_fn fn,
uintptr_t retaddr)
@@ -112,10 +122,10 @@ static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
int i;
for (i = 0; i < 2; i++) {
- const uint64_t a = s390_vec_read_element64(v2, i);
- const uint64_t b = s390_vec_read_element64(v3, i);
+ const float64 a = s390_vec_read_float64(v2, i);
+ const float64 b = s390_vec_read_float64(v3, i);
- s390_vec_write_element64(&tmp, i, fn(a, b, &env->fpu_status));
+ s390_vec_write_float64(&tmp, i, fn(a, b, &env->fpu_status));
vxc = check_ieee_exc(env, i, false, &vec_exc);
if (s || vxc) {
break;
@@ -125,22 +135,19 @@ static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
*v1 = tmp;
}
-static uint64_t vfa64(uint64_t a, uint64_t b, float_status *s)
-{
- return float64_add(a, b, s);
+#define DEF_GVEC_VOP3(NAME, OP) \
+void HELPER(gvec_##NAME##64)(void *v1, const void *v2, const void *v3, \
+ CPUS390XState *env, uint32_t desc) \
+{ \
+ const bool se = extract32(simd_data(desc), 3, 1); \
+ \
+ vop64_3(v1, v2, v3, env, se, float64_##OP, GETPC()); \
}
-void HELPER(gvec_vfa64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, false, vfa64, GETPC());
-}
-
-void HELPER(gvec_vfa64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, true, vfa64, GETPC());
-}
+DEF_GVEC_VOP3(vfa, add)
+DEF_GVEC_VOP3(vfs, sub)
+DEF_GVEC_VOP3(vfd, div)
+DEF_GVEC_VOP3(vfm, mul)
static int wfc64(const S390Vector *v1, const S390Vector *v2,
CPUS390XState *env, bool signal, uintptr_t retaddr)
@@ -376,23 +383,6 @@ void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC());
}
-static uint64_t vfd64(uint64_t a, uint64_t b, float_status *s)
-{
- return float64_div(a, b, s);
-}
-
-void HELPER(gvec_vfd64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, false, vfd64, GETPC());
-}
-
-void HELPER(gvec_vfd64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, true, vfd64, GETPC());
-}
-
static uint64_t vfi64(uint64_t a, float_status *s)
{
return float64_round_to_int(a, s);
@@ -494,23 +484,6 @@ void HELPER(gvec_vflr64s)(void *v1, const void *v2, CPUS390XState *env,
vflr64(v1, v2, env, true, XxC, erm, GETPC());
}
-static uint64_t vfm64(uint64_t a, uint64_t b, float_status *s)
-{
- return float64_mul(a, b, s);
-}
-
-void HELPER(gvec_vfm64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, false, vfm64, GETPC());
-}
-
-void HELPER(gvec_vfm64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, true, vfm64, GETPC());
-}
-
static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
const S390Vector *v4, CPUS390XState *env, bool s, int flags,
uintptr_t retaddr)
@@ -576,23 +549,6 @@ void HELPER(gvec_vfsq64s)(void *v1, const void *v2, CPUS390XState *env,
vop64_2(v1, v2, env, true, false, 0, vfsq64, GETPC());
}
-static uint64_t vfs64(uint64_t a, uint64_t b, float_status *s)
-{
- return float64_sub(a, b, s);
-}
-
-void HELPER(gvec_vfs64)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, false, vfs64, GETPC());
-}
-
-void HELPER(gvec_vfs64s)(void *v1, const void *v2, const void *v3,
- CPUS390XState *env, uint32_t desc)
-{
- vop64_3(v1, v2, v3, env, true, vfs64, GETPC());
-}
-
static int vftci64(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
bool s, uint16_t i3)
{
--
2.31.1
next prev parent reply other threads:[~2021-05-17 14:33 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 14:27 [PATCH v2 00/26] s390x/tcg: Implement Vector enhancements facility and switch to z14 David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 01/26] s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling David Hildenbrand
2021-06-01 21:27 ` Richard Henderson
2021-06-02 9:50 ` David Hildenbrand
2021-06-07 8:04 ` David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 02/26] s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED) David Hildenbrand
2021-06-01 21:27 ` Richard Henderson
2021-05-17 14:27 ` David Hildenbrand [this message]
2021-06-03 17:10 ` [PATCH v2 03/26] s390x/tcg: Simplify vop64_3() handling Richard Henderson
2021-05-17 14:27 ` [PATCH v2 04/26] s390x/tcg: Simplify vop64_2() handling David Hildenbrand
2021-06-03 17:16 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 05/26] s390x/tcg: Simplify vfc64() handling David Hildenbrand
2021-06-03 17:18 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 06/26] s390x/tcg: Simplify vftci64() handling David Hildenbrand
2021-06-03 17:21 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 07/26] s390x/tcg: Simplify vfma64() handling David Hildenbrand
2021-06-03 17:22 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 08/26] s390x/tcg: Simplify vfll32() handling David Hildenbrand
2021-06-03 17:23 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 09/26] s390x/tcg: Simplify vflr64() handling David Hildenbrand
2021-06-03 17:25 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 10/26] s390x/tcg: Simplify wfc64() handling David Hildenbrand
2021-06-03 17:27 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 11/26] s390x/tcg: Implement VECTOR BIT PERMUTE David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 12/26] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 13/26] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT) David Hildenbrand
2021-06-03 17:32 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 14/26] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT) David Hildenbrand
2021-06-03 17:33 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 15/26] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE * David Hildenbrand
2021-06-03 17:37 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 16/26] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR David Hildenbrand
2021-06-03 17:40 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 17/26] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 18/26] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 19/26] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 20/26] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE David Hildenbrand
2021-06-03 17:43 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 21/26] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
2021-06-03 17:44 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 22/26] s390x/tcg: Implement VECTOR FP NEGATIVE " David Hildenbrand
2021-06-03 17:45 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 23/26] softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag) David Hildenbrand
2021-06-03 17:01 ` Richard Henderson
2021-05-17 14:27 ` [PATCH v2 24/26] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM) David Hildenbrand
2021-06-03 18:13 ` Richard Henderson
2021-06-07 9:06 ` David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 25/26] s390x/tcg: We support Vector enhancements facility David Hildenbrand
2021-06-07 7:47 ` David Hildenbrand
2021-05-17 14:27 ` [PATCH v2 26/26] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2 David Hildenbrand
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