From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 35/48] target/ppc: Use MMUAccessType in mmu-radix64.c
Date: Wed, 19 May 2021 22:51:35 +1000 [thread overview]
Message-ID: <20210519125148.27720-36-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210519125148.27720-1-david@gibson.dropbear.id.au>
From: Richard Henderson <richard.henderson@linaro.org>
We must leave the 'int rwx' parameter to ppc_radix64_handle_mmu_fault
for now, but will clean that up later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210518201146.794854-3-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-radix64.c | 119 ++++++++++++++++++++++++---------------
1 file changed, 74 insertions(+), 45 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 646b9afb7b..7972153f23 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -75,71 +75,94 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
return true;
}
-static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr)
+static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type,
+ vaddr eaddr)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- if (rwx == 2) { /* Instruction Segment Interrupt */
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ /* Instruction Segment Interrupt */
cs->exception_index = POWERPC_EXCP_ISEG;
- } else { /* Data Segment Interrupt */
+ break;
+ case MMU_DATA_STORE:
+ case MMU_DATA_LOAD:
+ /* Data Segment Interrupt */
cs->exception_index = POWERPC_EXCP_DSEG;
env->spr[SPR_DAR] = eaddr;
+ break;
+ default:
+ g_assert_not_reached();
}
env->error_code = 0;
}
-static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
- uint32_t cause)
+static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type,
+ vaddr eaddr, uint32_t cause)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- if (rwx == 2) { /* Instruction Storage Interrupt */
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ /* Instruction Storage Interrupt */
cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = cause;
- } else { /* Data Storage Interrupt */
+ break;
+ case MMU_DATA_STORE:
+ cause |= DSISR_ISSTORE;
+ /* fall through */
+ case MMU_DATA_LOAD:
+ /* Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_DSI;
- if (rwx == 1) { /* Write -> Store */
- cause |= DSISR_ISSTORE;
- }
env->spr[SPR_DSISR] = cause;
env->spr[SPR_DAR] = eaddr;
env->error_code = 0;
+ break;
+ default:
+ g_assert_not_reached();
}
}
-static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr,
- hwaddr g_raddr, uint32_t cause)
+static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type,
+ vaddr eaddr, hwaddr g_raddr, uint32_t cause)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- if (rwx == 2) { /* H Instruction Storage Interrupt */
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ /* H Instruction Storage Interrupt */
cs->exception_index = POWERPC_EXCP_HISI;
env->spr[SPR_ASDR] = g_raddr;
env->error_code = cause;
- } else { /* H Data Storage Interrupt */
+ break;
+ case MMU_DATA_STORE:
+ cause |= DSISR_ISSTORE;
+ /* fall through */
+ case MMU_DATA_LOAD:
+ /* H Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_HDSI;
- if (rwx == 1) { /* Write -> Store */
- cause |= DSISR_ISSTORE;
- }
env->spr[SPR_HDSISR] = cause;
env->spr[SPR_HDAR] = eaddr;
env->spr[SPR_ASDR] = g_raddr;
env->error_code = 0;
+ break;
+ default:
+ g_assert_not_reached();
}
}
-static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
- int *fault_cause, int *prot,
+static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,
+ uint64_t pte, int *fault_cause, int *prot,
bool partition_scoped)
{
CPUPPCState *env = &cpu->env;
int need_prot;
/* Check Page Attributes (pte58:59) */
- if (((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO) && (rwx == 2)) {
+ if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) {
/*
* Radix PTE entries with the non-idempotent I/O attribute are treated
* as guarded storage
@@ -159,7 +182,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
}
/* Check if requested access type is allowed */
- need_prot = prot_for_access_type(rwx);
+ need_prot = prot_for_access_type(access_type);
if (need_prot & ~*prot) { /* Page Protected for that Access */
*fault_cause |= DSISR_PROTFAULT;
return true;
@@ -168,15 +191,15 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
return false;
}
-static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
- hwaddr pte_addr, int *prot)
+static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type,
+ uint64_t pte, hwaddr pte_addr, int *prot)
{
CPUState *cs = CPU(cpu);
uint64_t npte;
npte = pte | R_PTE_R; /* Always set reference bit */
- if (rwx == 1) { /* Store/Write */
+ if (access_type == MMU_DATA_STORE) { /* Store/Write */
npte |= R_PTE_C; /* Set change bit */
} else {
/*
@@ -271,7 +294,8 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
return true;
}
-static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
+static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
+ MMUAccessType access_type,
vaddr eaddr, hwaddr g_raddr,
ppc_v3_pate_t pate,
hwaddr *h_raddr, int *h_prot,
@@ -287,24 +311,25 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
&pte, &fault_cause, &pte_addr) ||
- ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) {
+ ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, h_prot, true)) {
if (pde_addr) { /* address being translated was that of a guest pde */
fault_cause |= DSISR_PRTABLE_FAULT;
}
if (guest_visible) {
- ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause);
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, fault_cause);
}
return 1;
}
if (guest_visible) {
- ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot);
+ ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot);
}
return 0;
}
-static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
+static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
+ MMUAccessType access_type,
vaddr eaddr, uint64_t pid,
ppc_v3_pate_t pate, hwaddr *g_raddr,
int *g_prot, int *g_page_size,
@@ -323,7 +348,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
if (offset >= size) {
/* offset exceeds size of the process table */
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
}
return 1;
}
@@ -364,7 +389,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
if (ret) {
/* No valid PTE */
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
}
return ret;
}
@@ -393,7 +418,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
if (ret) {
/* No valid pte */
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
}
return ret;
}
@@ -407,16 +432,16 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
*g_raddr = (rpn & ~mask) | (eaddr & mask);
}
- if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
+ if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, g_prot, false)) {
/* Access denied due to protection */
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause);
}
return 1;
}
if (guest_visible) {
- ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
+ ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot);
}
return 0;
@@ -439,7 +464,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
* | = On | Process Scoped | Scoped |
* +-------------+----------------+---------------+
*/
-static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
+static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
+ MMUAccessType access_type,
bool relocation,
hwaddr *raddr, int *psizep, int *protp,
bool guest_visible)
@@ -453,7 +479,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
/* Virtual Mode Access - get the fully qualified address */
if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
if (guest_visible) {
- ppc_radix64_raise_segi(cpu, rwx, eaddr);
+ ppc_radix64_raise_segi(cpu, access_type, eaddr);
}
return 1;
}
@@ -466,13 +492,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
} else {
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
}
return 1;
}
if (!validate_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
+ ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
}
return 1;
}
@@ -490,7 +516,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
* - Translates an effective address to a guest real address.
*/
if (relocation) {
- int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
+ int ret = ppc_radix64_process_scoped_xlate(cpu, access_type, eaddr, pid,
pate, &g_raddr, &prot,
&psize, guest_visible);
if (ret) {
@@ -513,9 +539,10 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
if (lpid || !msr_hv) {
int ret;
- ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr,
- pate, raddr, &prot, &psize,
- false, guest_visible);
+ ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr,
+ g_raddr, pate, raddr,
+ &prot, &psize, false,
+ guest_visible);
if (ret) {
return ret;
}
@@ -536,12 +563,14 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
CPUPPCState *env = &cpu->env;
int page_size, prot;
bool relocation;
+ MMUAccessType access_type;
hwaddr raddr;
assert(!(msr_hv && cpu->vhyp));
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
+ access_type = rwx;
- relocation = ((rwx == 2) && (msr_ir == 1)) || ((rwx != 2) && (msr_dr == 1));
+ relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
/* HV or virtual hypervisor Real Mode Access */
if (!relocation && (msr_hv || cpu->vhyp)) {
/* In real mode top 4 effective addr bits (mostly) ignored */
@@ -570,7 +599,7 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
}
/* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
- if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
+ if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr,
&page_size, &prot, true)) {
return 1;
}
--
2.31.1
next prev parent reply other threads:[~2021-05-19 13:26 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 12:51 [PULL 00/48] ppc-for-6.1 queue 20210519 David Gibson
2021-05-19 12:51 ` [PULL 01/48] hw/ppc/spapr.c: Extract MMU mode error reporting into a function David Gibson
2021-05-19 12:51 ` [PULL 02/48] hw/ppc/spapr.c: Make sure the host supports the selected MMU mode David Gibson
2021-05-19 12:51 ` [PULL 03/48] target/ppc: Fold gen_*_xer into their callers David Gibson
2021-05-19 12:51 ` [PULL 04/48] target/ppc: renamed SPR registration functions David Gibson
2021-05-19 12:51 ` [PULL 05/48] target/ppc: move SPR R/W callbacks to translate.c David Gibson
2021-05-19 12:51 ` [PULL 06/48] hw/ppc: moved hcalls that depend on softmmu David Gibson
2021-05-19 12:51 ` [PULL 07/48] target/ppc: moved function out of mmu-hash64 David Gibson
2021-05-19 12:51 ` [PULL 08/48] target/ppc: moved ppc_store_lpcr to misc_helper.c David Gibson
2021-05-19 12:51 ` [PULL 09/48] hw/ppc: moved has_spr to cpu.h David Gibson
2021-05-19 12:51 ` [PULL 10/48] target/ppc: turned SPR R/W callbacks not static David Gibson
2021-05-19 12:51 ` [PULL 11/48] target/ppc: isolated cpu init from translation logic David Gibson
2021-05-19 12:51 ` [PULL 12/48] target/ppc: created ppc_{store, get}_vscr for generic vscr usage David Gibson
2021-05-19 12:51 ` [PULL 13/48] target/ppc: updated vscr manipulation in machine.c David Gibson
2021-05-19 12:51 ` [PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c David Gibson
2021-05-19 12:51 ` [PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c David Gibson
2021-05-19 12:51 ` [PULL 16/48] target/ppc: Add cia field to DisasContext David Gibson
2021-05-19 12:51 ` [PULL 17/48] target/ppc: Split out decode_legacy David Gibson
2021-05-19 12:51 ` [PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception* David Gibson
2021-05-19 12:51 ` [PULL 19/48] target/ppc: Remove special case for POWERPC_SYSCALL David Gibson
2021-05-19 12:51 ` [PULL 20/48] target/ppc: Remove special case for POWERPC_EXCP_TRAP David Gibson
2021-05-19 12:51 ` [PULL 21/48] target/ppc: Simplify gen_debug_exception David Gibson
2021-05-19 12:51 ` [PULL 22/48] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE} David Gibson
2021-05-19 12:51 ` [PULL 23/48] target/ppc: Replace POWERPC_EXCP_SYNC with DISAS_EXIT David Gibson
2021-05-19 12:51 ` [PULL 24/48] target/ppc: Remove unnecessary gen_io_end calls David Gibson
2021-05-19 12:51 ` [PULL 25/48] target/ppc: Introduce gen_icount_io_start David Gibson
2021-05-19 12:51 ` [PULL 26/48] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE David Gibson
2021-05-19 12:51 ` [PULL 27/48] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN David Gibson
2021-05-19 12:51 ` [PULL 28/48] target/ppc: Remove DisasContext.exception David Gibson
2021-05-19 12:51 ` [PULL 29/48] target/ppc: Move single-step check to ppc_tr_tb_stop David Gibson
2021-05-19 12:51 ` [PULL 30/48] target/ppc: Tidy exception vs exit_tb David Gibson
2021-05-19 12:51 ` [PULL 31/48] target/ppc: Mark helper_raise_exception* as noreturn David Gibson
2021-05-19 12:51 ` [PULL 32/48] target/ppc: Use translator_loop_temp_check David Gibson
2021-05-19 12:51 ` [PULL 33/48] target/ppc: Fix load endianness for lxvwsx/lxvdsx David Gibson
2021-05-19 12:51 ` [PULL 34/48] target/ppc: Introduce prot_for_access_type David Gibson
2021-05-19 12:51 ` David Gibson [this message]
2021-05-19 12:51 ` [PULL 36/48] target/ppc: Use MMUAccessType in mmu-hash64.c David Gibson
2021-05-19 12:51 ` [PULL 37/48] target/ppc: Use MMUAccessType in mmu-hash32.c David Gibson
2021-05-19 12:51 ` [PULL 38/48] target/ppc: Rename access_type to type in mmu_helper.c David Gibson
2021-05-19 12:51 ` [PULL 39/48] target/ppc: Use MMUAccessType " David Gibson
2021-05-19 12:51 ` [PULL 40/48] target/ppc: Remove type argument from check_prot David Gibson
2021-05-19 12:51 ` [PULL 41/48] target/ppc: Remove type argument from ppc6xx_tlb_pte_check David Gibson
2021-05-19 12:51 ` [PULL 42/48] target/ppc: Remove type argument from ppc6xx_tlb_check David Gibson
2021-05-19 12:51 ` [PULL 43/48] target/ppc: Remove type argument from get_bat_6xx_tlb David Gibson
2021-05-19 12:51 ` [PULL 44/48] target/ppc: Remove type argument from mmu40x_get_physical_address David Gibson
2021-05-19 12:51 ` [PULL 45/48] target/ppc: Remove type argument from mmubooke_check_tlb David Gibson
2021-05-19 12:51 ` [PULL 46/48] target/ppc: Remove type argument from mmubooke_get_physical_address David Gibson
2021-05-19 12:51 ` [PULL 47/48] target/ppc: Remove type argument from mmubooke206_check_tlb David Gibson
2021-05-19 12:51 ` [PULL 48/48] target/ppc: Remove type argument for mmubooke206_get_physical_address David Gibson
2021-05-19 13:46 ` [PULL 00/48] ppc-for-6.1 queue 20210519 no-reply
2021-05-20 0:42 ` David Gibson
2021-05-20 9:00 ` Peter Maydell
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