From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57686C433ED for ; Wed, 19 May 2021 17:50:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0078F61244 for ; Wed, 19 May 2021 17:50:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0078F61244 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljQLH-0003Lj-50 for qemu-devel@archiver.kernel.org; Wed, 19 May 2021 13:50:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59534) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQIx-0001gO-Dt for qemu-devel@nongnu.org; Wed, 19 May 2021 13:48:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:44838) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljQIp-0006yp-V9 for qemu-devel@nongnu.org; Wed, 19 May 2021 13:48:23 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 232EC611BF; Wed, 19 May 2021 17:48:11 +0000 (UTC) Date: Wed, 19 May 2021 18:48:08 +0100 From: Catalin Marinas To: Steven Price Subject: Re: [PATCH v12 3/8] arm64: mte: Sync tags for pages where PTE is untagged Message-ID: <20210519174808.GD21619@arm.com> References: <20210517123239.8025-1-steven.price@arm.com> <20210517123239.8025-4-steven.price@arm.com> <87y2cdtk09.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=198.145.29.99; envelope-from=cmarinas@kernel.org; helo=mail.kernel.org X-Spam_score_int: -66 X-Spam_score: -6.7 X-Spam_bar: ------ X-Spam_report: (-6.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Peter Maydell , "Dr. David Alan Gilbert" , Andrew Jones , Haibo Xu , Suzuki K Poulose , qemu-devel@nongnu.org, Marc Zyngier , Juan Quintela , Richard Henderson , linux-kernel@vger.kernel.org, Dave Martin , James Morse , linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, May 19, 2021 at 10:32:01AM +0100, Steven Price wrote: > On 17/05/2021 17:14, Marc Zyngier wrote: > > On Mon, 17 May 2021 13:32:34 +0100, > > Steven Price wrote: > >> > >> A KVM guest could store tags in a page even if the VMM hasn't mapped > >> the page with PROT_MTE. So when restoring pages from swap we will > >> need to check to see if there are any saved tags even if !pte_tagged(). > >> > >> However don't check pages for which pte_access_permitted() returns false > >> as these will not have been swapped out. > >> > >> Signed-off-by: Steven Price > >> --- > >> arch/arm64/include/asm/pgtable.h | 9 +++++++-- > >> arch/arm64/kernel/mte.c | 16 ++++++++++++++-- > >> 2 files changed, 21 insertions(+), 4 deletions(-) > >> > >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > >> index 0b10204e72fc..275178a810c1 100644 > >> --- a/arch/arm64/include/asm/pgtable.h > >> +++ b/arch/arm64/include/asm/pgtable.h > >> @@ -314,8 +314,13 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, > >> if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) > >> __sync_icache_dcache(pte); > >> > >> - if (system_supports_mte() && > >> - pte_present(pte) && pte_tagged(pte) && !pte_special(pte)) > >> + /* > >> + * If the PTE would provide user space access to the tags associated > >> + * with it then ensure that the MTE tags are synchronised. Exec-only > >> + * mappings don't expose tags (instruction fetches don't check tags). > > > > I'm not sure I understand this comment. Of course, execution doesn't > > match tags. But the memory could still have tags associated with > > it. Does this mean such a page would lose its tags is swapped out? > > Hmm, I probably should have reread that - the context of the comment is > lost. > > I added the comment when changing to pte_access_permitted(), and the > comment on pte_access_permitted() explains a potential gotcha: > > * p??_access_permitted() is true for valid user mappings (PTE_USER > * bit set, subject to the write permission check). For execute-only > * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits > * not set) must return false. PROT_NONE mappings do not have the > * PTE_VALID bit set. > > So execute-only mappings return false even though that is effectively a > type of user access. However, because MTE checks are not performed by > the PE for instruction fetches this doesn't matter. I'll update the > comment, how about: > > /* > * If the PTE would provide user space access to the tags associated > * with it then ensure that the MTE tags are synchronised. Although > * pte_access_permitted() returns false for exec only mappings, they > * don't expose tags (instruction fetches don't check tags). > */ This looks fine to me. We basically want to check the PTE_VALID and PTE_USER bits and pte_access_permitted() does this (we could come up with a new macro name like pte_valid_user() but since we don't care about execute-only, it gets unnecessarily complicated). -- Catalin