From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: [PULL 39/50] target/i386: Cleanup read_crN, write_crN, lmsw
Date: Wed, 19 May 2021 13:30:39 -0500 [thread overview]
Message-ID: <20210519183050.875453-40-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210519183050.875453-1-richard.henderson@linaro.org>
Pull the svm intercept check into the translator.
Pull the entire implementation of lmsw into the translator.
Push the check for CR8LEG into the regno validation switch.
Unify the gen_io_start check between read/write.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210514151342.384376-40-richard.henderson@linaro.org>
---
target/i386/helper.h | 5 +-
target/i386/tcg/misc_helper.c | 8 ---
target/i386/tcg/sysemu/misc_helper.c | 2 -
target/i386/tcg/translate.c | 97 +++++++++++++++-------------
4 files changed, 54 insertions(+), 58 deletions(-)
diff --git a/target/i386/helper.h b/target/i386/helper.h
index 86484a4ec4..ebfaca66dd 100644
--- a/target/i386/helper.h
+++ b/target/i386/helper.h
@@ -42,9 +42,8 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl)
DEF_HELPER_2(iret_real, void, env, int)
DEF_HELPER_3(iret_protected, void, env, int, int)
DEF_HELPER_3(lret_protected, void, env, int, int)
-DEF_HELPER_2(read_crN, tl, env, int)
-DEF_HELPER_3(write_crN, void, env, int, tl)
-DEF_HELPER_2(lmsw, void, env, tl)
+DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int)
+DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl)
DEF_HELPER_1(clts, void, env)
#ifndef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index 0e9a4f0bfc..931dbd9db0 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env)
env->regs[R_EDX] = edx;
}
-void helper_lmsw(CPUX86State *env, target_ulong t0)
-{
- /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
- if already set to one. */
- t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
- helper_write_crN(env, 0, t0);
-}
-
void helper_invlpg(CPUX86State *env, target_ulong addr)
{
X86CPU *cpu = env_archcpu(env);
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 66e7939537..c7381ef7e8 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -65,7 +65,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
{
target_ulong val;
- cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC());
switch (reg) {
default:
val = env->cr[reg];
@@ -83,7 +82,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
{
- cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC());
switch (reg) {
case 0:
cpu_x86_update_cr0(env, t0);
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 3844c0342e..14a44a00ca 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7654,13 +7654,22 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64);
break;
+
CASE_MODRM_OP(6): /* lmsw */
if (!check_cpl0(s)) {
break;
}
gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
- gen_helper_lmsw(cpu_env, s->T0);
+ /*
+ * Only the 4 lower bits of CR0 are modified.
+ * PE cannot be set to zero if already set to one.
+ */
+ tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0]));
+ tcg_gen_andi_tl(s->T0, s->T0, 0xf);
+ tcg_gen_andi_tl(s->T1, s->T1, ~0xe);
+ tcg_gen_or_tl(s->T0, s->T0, s->T1);
+ gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0);
gen_jmp_im(s, s->pc - s->cs_base);
gen_eob(s);
break;
@@ -8034,58 +8043,56 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
modrm = x86_ldub_code(env, s);
gen_nop_modrm(env, s, modrm);
break;
+
case 0x120: /* mov reg, crN */
case 0x122: /* mov crN, reg */
- if (check_cpl0(s)) {
- modrm = x86_ldub_code(env, s);
- /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
- * AMD documentation (24594.pdf) and testing of
- * intel 386 and 486 processors all show that the mod bits
- * are assumed to be 1's, regardless of actual values.
- */
- rm = (modrm & 7) | REX_B(s);
- reg = ((modrm >> 3) & 7) | REX_R(s);
- if (CODE64(s))
- ot = MO_64;
- else
- ot = MO_32;
- if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
+ if (!check_cpl0(s)) {
+ break;
+ }
+ modrm = x86_ldub_code(env, s);
+ /*
+ * Ignore the mod bits (assume (modrm&0xc0)==0xc0).
+ * AMD documentation (24594.pdf) and testing of Intel 386 and 486
+ * processors all show that the mod bits are assumed to be 1's,
+ * regardless of actual values.
+ */
+ rm = (modrm & 7) | REX_B(s);
+ reg = ((modrm >> 3) & 7) | REX_R(s);
+ switch (reg) {
+ case 0:
+ if ((prefixes & PREFIX_LOCK) &&
(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
reg = 8;
}
- switch(reg) {
- case 0:
- case 2:
- case 3:
- case 4:
- case 8:
- gen_update_cc_op(s);
- gen_jmp_im(s, pc_start - s->cs_base);
- if (b & 2) {
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_op_mov_v_reg(s, ot, s->T0, rm);
- gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
- s->T0);
- gen_jmp_im(s, s->pc - s->cs_base);
- gen_eob(s);
- } else {
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_read_crN(s->T0, cpu_env, tcg_const_i32(reg));
- gen_op_mov_reg_v(s, ot, rm, s->T0);
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
- gen_jmp(s, s->pc - s->cs_base);
- }
- }
- break;
- default:
- goto unknown_op;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ break;
+ default:
+ goto unknown_op;
+ }
+ ot = (CODE64(s) ? MO_64 : MO_32);
+
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ if (b & 2) {
+ gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg);
+ gen_op_mov_v_reg(s, ot, s->T0, rm);
+ gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0);
+ gen_jmp_im(s, s->pc - s->cs_base);
+ gen_eob(s);
+ } else {
+ gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg);
+ gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg));
+ gen_op_mov_reg_v(s, ot, rm, s->T0);
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+ gen_jmp(s, s->pc - s->cs_base);
}
}
break;
+
case 0x121: /* mov reg, drN */
case 0x123: /* mov drN, reg */
if (check_cpl0(s)) {
--
2.25.1
next prev parent reply other threads:[~2021-05-19 18:54 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 18:30 [PULL 00/50] target/i386 translate cleanups Richard Henderson
2021-05-19 18:30 ` [PULL 01/50] target/i386: Split out gen_exception_gpf Richard Henderson
2021-05-19 18:30 ` [PULL 02/50] target/i386: Split out check_cpl0 Richard Henderson
2021-05-19 18:30 ` [PULL 03/50] target/i386: Unify code paths for IRET Richard Henderson
2021-05-19 18:30 ` [PULL 04/50] target/i386: Split out check_vm86_iopl Richard Henderson
2021-05-19 18:30 ` [PULL 05/50] target/i386: Split out check_iopl Richard Henderson
2021-05-19 18:30 ` [PULL 06/50] target/i386: Assert PE is set for user-only Richard Henderson
2021-05-19 18:30 ` [PULL 07/50] target/i386: Assert CPL is 3 " Richard Henderson
2021-05-19 18:30 ` [PULL 08/50] target/i386: Assert IOPL is 0 " Richard Henderson
2021-05-19 18:30 ` [PULL 09/50] target/i386: Assert !VM86 for x86_64 user-only Richard Henderson
2021-05-19 18:30 ` [PULL 10/50] target/i386: Assert CODE32 " Richard Henderson
2021-05-19 18:30 ` [PULL 11/50] target/i386: Assert SS32 " Richard Henderson
2021-05-19 18:30 ` [PULL 12/50] target/i386: Assert CODE64 " Richard Henderson
2021-05-19 18:30 ` [PULL 13/50] target/i386: Assert LMA " Richard Henderson
2021-05-19 18:30 ` [PULL 14/50] target/i386: Assert !ADDSEG " Richard Henderson
2021-05-19 18:30 ` [PULL 15/50] target/i386: Introduce REX_PREFIX Richard Henderson
2021-05-19 18:30 ` [PULL 16/50] target/i386: Tidy REX_B, REX_X definition Richard Henderson
2021-05-19 18:30 ` [PULL 17/50] target/i386: Move rex_r into DisasContext Richard Henderson
2021-05-19 18:30 ` [PULL 18/50] target/i386: Move rex_w " Richard Henderson
2021-05-19 18:30 ` [PULL 19/50] target/i386: Remove DisasContext.f_st as unused Richard Henderson
2021-05-19 18:30 ` [PULL 20/50] target/i386: Reduce DisasContext.flags to uint32_t Richard Henderson
2021-05-19 18:30 ` [PULL 21/50] target/i386: Reduce DisasContext.override to int8_t Richard Henderson
2021-05-19 18:30 ` [PULL 22/50] target/i386: Reduce DisasContext.prefix to uint8_t Richard Henderson
2021-05-19 18:30 ` [PULL 23/50] target/i386: Reduce DisasContext.vex_[lv] " Richard Henderson
2021-05-19 18:30 ` [PULL 24/50] target/i386: Reduce DisasContext popl_esp_hack and rip_offset " Richard Henderson
2021-05-19 18:30 ` [PULL 25/50] target/i386: Leave TF in DisasContext.flags Richard Henderson
2021-05-19 18:30 ` [PULL 26/50] target/i386: Reduce DisasContext jmp_opt, repz_opt to bool Richard Henderson
2021-05-19 18:30 ` [PULL 27/50] target/i386: Fix the comment for repz_opt Richard Henderson
2021-05-19 18:30 ` [PULL 28/50] target/i386: Reorder DisasContext members Richard Henderson
2021-05-19 18:30 ` [PULL 29/50] target/i386: Add stub generator for helper_set_dr Richard Henderson
2021-05-19 18:30 ` [PULL 30/50] target/i386: Assert !SVME for user-only Richard Henderson
2021-05-19 18:30 ` [PULL 31/50] target/i386: Assert !GUEST " Richard Henderson
2021-05-19 18:30 ` [PULL 32/50] target/i386: Implement skinit in translate.c Richard Henderson
2021-05-19 18:30 ` [PULL 33/50] target/i386: Eliminate SVM helpers for user-only Richard Henderson
2021-05-19 18:30 ` [PULL 34/50] target/i386: Mark some helpers as noreturn Richard Henderson
2021-05-19 18:30 ` [PULL 35/50] target/i386: Simplify gen_debug usage Richard Henderson
2021-05-19 18:30 ` [PULL 36/50] target/i386: Tidy svm_check_intercept from tcg Richard Henderson
2021-05-19 18:30 ` [PULL 37/50] target/i386: Remove pc_start argument to gen_svm_check_intercept Richard Henderson
2021-05-19 18:30 ` [PULL 38/50] target/i386: Remove user stub for cpu_vmexit Richard Henderson
2021-05-19 18:30 ` Richard Henderson [this message]
2021-05-19 18:30 ` [PULL 40/50] target/i386: Pass env to do_pause and do_hlt Richard Henderson
2021-05-19 18:30 ` [PULL 41/50] target/i386: Move invlpg, hlt, monitor, mwait to sysemu Richard Henderson
2021-05-19 18:30 ` [PULL 42/50] target/i386: Unify invlpg, invlpga Richard Henderson
2021-05-19 18:30 ` [PULL 43/50] target/i386: Inline user cpu_svm_check_intercept_param Richard Henderson
2021-05-19 18:30 ` [PULL 44/50] target/i386: Eliminate user stubs for read/write_crN, rd/wrmsr Richard Henderson
2021-05-19 18:30 ` [PULL 45/50] target/i386: Exit tb after wrmsr Richard Henderson
2021-05-19 18:30 ` [PULL 46/50] target/i386: Tidy gen_check_io Richard Henderson
2021-05-19 18:30 ` [PULL 47/50] target/i386: Pass in port to gen_check_io Richard Henderson
2021-05-19 18:30 ` [PULL 48/50] target/i386: Create helper_check_io Richard Henderson
2021-05-19 18:30 ` [PULL 49/50] target/i386: Move helper_check_io to sysemu Richard Henderson
2021-05-19 18:30 ` [PULL 50/50] target/i386: Remove user-only i/o stubs Richard Henderson
2021-05-19 19:15 ` [PULL 00/50] target/i386 translate cleanups no-reply
2021-05-20 13:19 ` Peter Maydell
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