[PATCH 0/9] target/arm: MVE preliminaries

[Peter Maydell <peter.maydell@linaro.org>]

This patchset is a collection of easy preliminary MVE patches, which I
send out now just to try to avoid the MVE patchset landing as one
enormous series. These patches:
 * update feature checks on existing insns that should now check
   "if FP or MVE" rather than just "if FP"
 * fixes a minor non-guest-visible issue in fp_sysreg_checks()
 * adds support for reading and writing the MVE VPR register
 * makes FPSCR.LTPSIZE writable if MVE
 * makes FPSCR.QC exist for MVE
None of this code will be "live" yet, as no CPU sets the MVE ID
register fields.

The last patch is not MVE related but I've had it kicking about in a
private branch for a while now and it would be nice to have it
upstream even though we don't have an immediate in-tree use.  It just
makes the NS VTOR configurable by the board/SoC the same way the S
VTOR already is, which then matches the hardware.

thanks
-- PMM

Peter Maydell (9):
  target/arm: Add isar feature check functions for MVE
  target/arm: Update feature checks for insns which are "MVE or FP"
  target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp
  target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp
  target/arm: Fix return values in fp_sysreg_checks()
  target/arm: Implement M-profile VPR register
  target/arm: Make FPSCR.LTPSIZE writable for MVE
  target/arm: Enable FPSCR.QC bit for MVE
  target/arm: Allow board models to specify initial NS VTOR

 include/hw/arm/armv7m.h    |   2 +
 target/arm/cpu.h           |  33 ++++++++-
 hw/arm/armv7m.c            |   7 ++
 target/arm/cpu.c           |  10 +++
 target/arm/machine.c       |  20 ++++++
 target/arm/translate-vfp.c | 140 ++++++++++++++++++++++++++-----------
 target/arm/vfp_helper.c    |  12 ++--
 7 files changed, 179 insertions(+), 45 deletions(-)

-- 
2.20.1