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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id l20sm10268397pjq.38.2021.05.24.09.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 May 2021 09:10:04 -0700 (PDT) From: Richard Henderson To: peter.maydell@linaro.org Subject: Re: [PATCH] hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic Date: Mon, 24 May 2021 09:10:03 -0700 Message-Id: <20210524161003.18335-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510150016.24910-1-peter.maydell@linaro.org> References: <20210510150016.24910-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, ckim@etri.re.kr, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" > In icc_eoir_write() we assume that we can identify the group of the > IRQ being completed based purely on which register is being written > to and the current CPU state, and that "CPU state matches group > indicated by register" is the only necessary access check. > > This isn't correct: if the CPU is not in Secure state then EOIR1 will > only complete Group 1 NS IRQs, but if the CPU is in EL3 it can > complete both Group 1 S and Group 1 NS IRQs. (The pseudocode > ICC_EOIR1_EL1 makes this clear.) We were also missing the logic to > prevent EOIR0 writes completing G0 IRQs when they should not. > > Rearrange the logic to first identify the group of the current > highest priority interrupt and then look at whether we should > complete it or ignore the access based on which register was accessed > and the state of the CPU. The resulting behavioural change is: > * EL3 can now complete G1NS interrupts > * G0 interrupt completion is now ignored if the GIC > and the CPU have the security extension enabled and > the CPU is not secure > > Reported-by: Chan Kim > Signed-off-by: Peter Maydell > --- > hw/intc/arm_gicv3_cpuif.c | 48 ++++++++++++++++++++++++++------------- > 1 file changed, 32 insertions(+), 16 deletions(-) Reviewed-by: Richard Henderson r~