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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar
Date: Tue, 25 May 2021 16:07:29 +0100	[thread overview]
Message-ID: <20210525150736.32695-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210525150736.32695-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Cut and paste error from another pattern.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-86-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-neon.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 1a8fc7fb390..14a9d0d4d30 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -325,7 +325,6 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
 {
     gen_helper_gvec_4 *fn_gvec;
     int opr_sz;
-    TCGv_ptr fpst;
 
     if (!dc_isar_feature(aa32_dp, s)) {
         return false;
@@ -347,13 +346,11 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
 
     fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
     opr_sz = (1 + a->q) * 8;
-    fpst = fpstatus_ptr(FPST_STD);
     tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
                        vfp_reg_offset(1, a->vn),
                        vfp_reg_offset(1, a->rm),
                        vfp_reg_offset(1, a->vd),
                        opr_sz, opr_sz, a->index, fn_gvec);
-    tcg_temp_free_ptr(fpst);
     return true;
 }
 
-- 
2.20.1



  parent reply	other threads:[~2021-05-25 16:39 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25 15:07 [PULL 095/114] target/arm: Implement SVE2 FCVTLT Peter Maydell
2021-05-25 15:07 ` [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX Peter Maydell
2021-05-25 15:07 ` [PULL 097/114] target/arm: Implement SVE2 FLOGB Peter Maydell
2021-05-25 15:07 ` [PULL 098/114] target/arm: Share table of sve load functions Peter Maydell
2021-05-25 15:07 ` [PULL 099/114] target/arm: Tidy do_ldrq Peter Maydell
2021-05-25 15:07 ` [PULL 100/114] target/arm: Implement SVE2 LD1RO Peter Maydell
2021-05-25 15:07 ` [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN Peter Maydell
2021-05-25 15:07 ` [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate Peter Maydell
2021-05-25 15:07 ` [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h Peter Maydell
2021-05-25 15:07 ` [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long Peter Maydell
2021-05-25 15:07 ` [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT Peter Maydell
2021-05-25 15:07 ` [PULL 106/114] target/arm: Split out do_neon_ddda_fpst Peter Maydell
2021-05-25 15:07 ` Peter Maydell [this message]
2021-05-25 15:07 ` [PULL 108/114] target/arm: Fix decode for VDOT (indexed) Peter Maydell
2021-05-25 15:07 ` [PULL 109/114] target/arm: Split out do_neon_ddda Peter Maydell
2021-05-25 15:07 ` [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT Peter Maydell
2021-05-25 15:07 ` [PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT Peter Maydell
2021-05-25 15:07 ` [PULL 112/114] target/arm: Implement integer matrix multiply accumulate Peter Maydell
2021-05-25 15:07 ` [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions Peter Maydell
2021-05-25 15:07 ` [PULL 114/114] target/arm: Enable SVE2 " Peter Maydell

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