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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
Date: Wed, 26 May 2021 16:47:05 -0700	[thread overview]
Message-ID: <20210526234710.125396-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210526234710.125396-1-richard.henderson@linaro.org>

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-20-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h            | 3 ---
 include/hw/core/sysemu-cpu-ops.h | 5 +++++
 hw/core/cpu-sysemu.c             | 4 ++--
 target/arm/cpu.c                 | 2 +-
 target/i386/cpu.c                | 2 +-
 5 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 15b16d3f6d..af6246c905 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -109,8 +109,6 @@ struct SysemuCPUOps;
  *       associated memory transaction attributes to use for the access.
  *       CPUs which use memory transaction attributes should implement this
  *       instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- *       a memory access with the specified memory transaction attributes.
  * @gdb_read_register: Callback for letting GDB read a register.
  * @gdb_write_register: Callback for letting GDB write a register.
  * @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -152,7 +150,6 @@ struct CPUClass {
     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
     hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
                                         MemTxAttrs *attrs);
-    int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
     int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 52ac0ae4e1..8f8326e810 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
  * struct SysemuCPUOps: System operations specific to a CPU class
  */
 typedef struct SysemuCPUOps {
+    /**
+     * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+     *       a memory access with the specified memory transaction attributes.
+     */
+    int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
     /**
      * @get_crash_info: Callback for reporting guest crash information in
      * GUEST_PANICKED events.
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index d55ef8d23d..ba53c2eaa8 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -72,8 +72,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
     CPUClass *cc = CPU_GET_CLASS(cpu);
     int ret = 0;
 
-    if (cc->asidx_from_attrs) {
-        ret = cc->asidx_from_attrs(cpu, attrs);
+    if (cc->sysemu_ops->asidx_from_attrs) {
+        ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
         assert(ret < cpu->num_ases && ret >= 0);
     }
     return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 18627cc3c6..85666b765f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1948,6 +1948,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
 #include "hw/core/sysemu-cpu-ops.h"
 
 static const struct SysemuCPUOps arm_sysemu_ops = {
+    .asidx_from_attrs = arm_asidx_from_attrs,
     .write_elf32_note = arm_cpu_write_elf32_note,
     .write_elf64_note = arm_cpu_write_elf64_note,
     .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -1993,7 +1994,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_write_register = arm_cpu_gdb_write_register;
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
-    cc->asidx_from_attrs = arm_asidx_from_attrs;
     cc->sysemu_ops = &arm_sysemu_ops;
 #endif
     cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2ba82921d6..45e7ded0ce 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6718,6 +6718,7 @@ static Property x86_cpu_properties[] = {
 #include "hw/core/sysemu-cpu-ops.h"
 
 static const struct SysemuCPUOps i386_sysemu_ops = {
+    .asidx_from_attrs = x86_asidx_from_attrs,
     .get_crash_info = x86_cpu_get_crash_info,
     .write_elf32_note = x86_cpu_write_elf32_note,
     .write_elf64_note = x86_cpu_write_elf64_note,
@@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
 
 #ifndef CONFIG_USER_ONLY
-    cc->asidx_from_attrs = x86_asidx_from_attrs;
     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
     cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
     cc->sysemu_ops = &i386_sysemu_ops;
-- 
2.25.1



  parent reply	other threads:[~2021-05-26 23:58 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-26 23:46 [PULL 00/31] tcg patch queue Richard Henderson
2021-05-26 23:46 ` [PULL 01/31] exec/memory_ldst_cached: Sort declarations Richard Henderson
2021-05-26 23:46 ` [PULL 02/31] exec/memory_ldst_phys: " Richard Henderson
2021-05-26 23:46 ` [PULL 03/31] exec/memory_ldst: Use correct type sizes Richard Henderson
2021-05-26 23:46 ` [PULL 04/31] exec/memory_ldst_phys: " Richard Henderson
2021-05-26 23:46 ` [PULL 05/31] exec/memory_ldst_cached: Use correct type size Richard Henderson
2021-05-26 23:46 ` [PULL 06/31] exec/memory: " Richard Henderson
2021-05-26 23:46 ` [PULL 07/31] accel/tcg: Reduce 'exec/tb-context.h' inclusion Richard Henderson
2021-05-28 15:44   ` Philippe Mathieu-Daudé
2021-05-26 23:46 ` [PULL 08/31] accel/tcg: Keep TranslationBlock headers local to TCG Richard Henderson
2021-05-26 23:46 ` [PULL 09/31] replay: fix watchpoint processing for reverse debugging Richard Henderson
2021-05-26 23:46 ` [PULL 10/31] tcg/aarch64: Fix tcg_out_rotl Richard Henderson
2021-05-26 23:46 ` [PULL 11/31] cpu: Remove duplicated 'sysemu/hw_accel.h' header Richard Henderson
2021-05-26 23:46 ` [PULL 12/31] cpu: Split as cpu-common / cpu-sysemu Richard Henderson
2021-05-26 23:46 ` [PULL 13/31] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Richard Henderson
2021-05-26 23:46 ` [PULL 14/31] cpu: Introduce cpu_virtio_is_big_endian() Richard Henderson
2021-05-26 23:46 ` [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place Richard Henderson
2021-05-26 23:46 ` [PULL 16/31] cpu: Directly use get_paging_enabled() " Richard Henderson
2021-05-26 23:46 ` [PULL 17/31] cpu: Directly use get_memory_mapping() " Richard Henderson
2021-05-26 23:46 ` [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation Richard Henderson
2021-05-26 23:46 ` [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd Richard Henderson
2021-05-26 23:46 ` [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass Richard Henderson
2021-05-26 23:47 ` [PULL 21/31] cpu: Introduce SysemuCPUOps structure Richard Henderson
2021-05-26 23:47 ` [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps Richard Henderson
2021-05-26 23:47 ` [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian " Richard Henderson
2021-05-26 23:47 ` [PULL 24/31] cpu: Move CPUClass::get_crash_info " Richard Henderson
2021-05-26 23:47 ` [PULL 25/31] cpu: Move CPUClass::write_elf* " Richard Henderson
2021-05-26 23:47 ` Richard Henderson [this message]
2021-05-26 23:47 ` [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug " Richard Henderson
2021-05-26 23:47 ` [PULL 28/31] cpu: Move CPUClass::get_memory_mapping " Richard Henderson
2021-05-26 23:47 ` [PULL 29/31] cpu: Move CPUClass::get_paging_enabled " Richard Henderson
2021-05-26 23:47 ` [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Richard Henderson
2021-05-26 23:47 ` [PULL 31/31] hw/core: Constify TCGCPUOps Richard Henderson
2021-05-28 18:25 ` [PULL 00/31] tcg patch queue Peter Maydell

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