From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH] target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()
Date: Sun, 30 May 2021 11:45:37 +0200 [thread overview]
Message-ID: <20210530094538.1275329-1-f4bug@amsat.org> (raw)
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode.
Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c03a8ae1fed..84c71a75c76 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -20177,16 +20177,18 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
{
TCGv tv0 = tcg_temp_new();
TCGv tv1 = tcg_temp_new();
int16_t imm = extract32(ctx->opcode, 16, 7);
tcg_gen_movi_tl(tv0, rd >> 3);
tcg_gen_movi_tl(tv1, imm);
gen_helper_shilo(tv0, tv1, cpu_env);
+ tcg_temp_free(tv1);
+ tcg_temp_free(tv0);
}
break;
case NM_MULEQ_S_W_PHL:
check_dsp(ctx);
gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULEQ_S_W_PHR:
--
2.26.3
next reply other threads:[~2021-05-30 9:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-30 9:45 Philippe Mathieu-Daudé [this message]
2021-05-30 15:25 ` [PATCH] target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn() Richard Henderson
2021-06-19 18:02 ` Philippe Mathieu-Daudé
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