From: Jose Martins <josemartins90@gmail.com>
To: qemu-devel@nongnu.org
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Jose Martins <josemartins90@gmail.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 0/2] target/riscv: fix hypervisor exceptions
Date: Wed, 2 Jun 2021 20:11:23 +0100 [thread overview]
Message-ID: <20210602191125.525742-1-josemartins90@gmail.com> (raw)
This patch series fixes the forwarding of VS-level execptions to HS-mode and
removes unecessary code previously used for the routing of exceptions to
HS-mode.
Jose Martins (2):
target/riscv: fix VS interrupts forwarding to HS
target/riscv: remove force HS exception
target/riscv/cpu.h | 2 --
target/riscv/cpu_bits.h | 6 -----
target/riscv/cpu_helper.c | 54 +++++++--------------------------------
3 files changed, 9 insertions(+), 53 deletions(-)
--
2.30.2
next reply other threads:[~2021-06-02 19:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 19:11 Jose Martins [this message]
2021-06-02 19:11 ` [PATCH 1/2] target/riscv: fix VS interrupts forwarding to HS Jose Martins
2021-06-10 23:14 ` Alistair Francis
2021-06-02 19:11 ` [PATCH 2/2] target/riscv: remove force HS exception Jose Martins
2021-06-10 23:14 ` Alistair Francis
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