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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id f26sm1420082edu.31.2021.06.03.02.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 4/6] target/microblaze: Fix Exception Status Register 'Cause' definitions Date: Thu, 3 Jun 2021 11:03:08 +0200 Message-Id: <20210603090310.2749892-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Richard Henderson , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" See 'MicroBlaze Processor Reference Guide' UG081 (v9.0), Table 1-11: "Exception Status Register (ESR)". Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..42b9ad8d313 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -95,10 +95,10 @@ typedef struct CPUMBState CPUMBState; #define ESR_EC_FPU 6 #define ESR_EC_PRIVINSN 7 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ -#define ESR_EC_DATA_STORAGE 8 -#define ESR_EC_INSN_STORAGE 9 -#define ESR_EC_DATA_TLB 10 -#define ESR_EC_INSN_TLB 11 +#define ESR_EC_DATA_STORAGE 16 +#define ESR_EC_INSN_STORAGE 17 +#define ESR_EC_DATA_TLB 18 +#define ESR_EC_INSN_TLB 19 #define ESR_EC_MASK 31 /* Floating Point Status Register (FSR) Bits */ -- 2.26.3