From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
Date: Fri, 4 Jun 2021 13:12:04 -0700 [thread overview]
Message-ID: <20210604201210.920136-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210604201210.920136-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index cfbadad72c..94d768f249 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -166,7 +166,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index d21aaab6f7..b94e6ed0f3 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -183,6 +183,7 @@ typedef enum {
INSN_VORN = 0xf2300110,
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
+ INSN_VMUL = 0xf2000910,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@@ -2394,6 +2395,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
@@ -2755,6 +2757,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
+ case INDEX_op_mul_vec:
+ tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
+ return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
@@ -2871,6 +2876,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_neg_vec:
return vece < MO_64;
default:
--
2.25.1
next prev parent reply other threads:[~2021-06-04 20:18 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 20:11 [PULL 00/15] tcg patch queue Richard Henderson
2021-06-04 20:11 ` [PULL 01/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
2021-06-04 20:11 ` [PULL 02/15] tcg/arm: Add host vector framework Richard Henderson
2021-06-04 20:11 ` [PULL 03/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
2021-06-04 20:11 ` [PULL 04/15] tcg/arm: Implement tcg_out_mov " Richard Henderson
2021-06-04 20:12 ` [PULL 05/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
2021-06-04 20:12 ` [PULL 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
2021-06-04 20:12 ` [PULL 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
2021-06-04 20:12 ` [PULL 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
2021-06-04 20:12 ` Richard Henderson [this message]
2021-06-04 20:12 ` [PULL 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-06-04 20:12 ` [PULL 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-06-04 20:12 ` [PULL 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-06-04 20:12 ` [PULL 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
2021-06-04 20:12 ` [PULL 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Richard Henderson
2021-06-04 20:12 ` [PULL 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson
2021-06-05 15:11 ` [PULL 00/15] tcg patch queue Peter Maydell
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