From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PULL 04/15] tcg/arm: Implement tcg_out_mov for vector types
Date: Fri, 4 Jun 2021 13:11:59 -0700 [thread overview]
Message-ID: <20210604201210.920136-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210604201210.920136-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
1 file changed, 46 insertions(+), 6 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index c6cfb83308..a802d4b585 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -173,6 +173,8 @@ typedef enum {
/* Otherwise the assembler uses mov r0,r0 */
INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
+ INSN_VORR = 0xf2200110,
+
INSN_VLD1 = 0xf4200000, /* VLD1 (multiple single elements) */
INSN_VST1 = 0xf4000000, /* VST1 (multiple single elements) */
} ARMInsn;
@@ -1106,6 +1108,25 @@ static uint32_t encode_vd(TCGReg rd)
return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
}
+static uint32_t encode_vn(TCGReg rn)
+{
+ tcg_debug_assert(rn >= TCG_REG_Q0);
+ return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+ tcg_debug_assert(rm >= TCG_REG_Q0);
+ return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+ TCGReg d, TCGReg n, TCGReg m)
+{
+ tcg_out32(s, insn | (vece << 20) | (q << 6) |
+ encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
TCGReg rd, TCGReg rn, int offset)
{
@@ -2276,16 +2297,35 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false;
}
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_out_mov_reg(s, COND_AL, ret, arg);
- return true;
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+ tcg_out_mov_reg(s, COND_AL, ret, arg);
+ return true;
+ }
+ return false;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ /* "VMOV D,N" is an alias for "VORR D,N,N". */
+ tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
+ return true;
+
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ tcg_debug_assert(type == TCG_TYPE_I32);
+ tcg_debug_assert(ret < TCG_REG_Q0);
tcg_out_movi32(s, COND_AL, ret, arg);
}
--
2.25.1
next prev parent reply other threads:[~2021-06-04 20:15 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 20:11 [PULL 00/15] tcg patch queue Richard Henderson
2021-06-04 20:11 ` [PULL 01/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
2021-06-04 20:11 ` [PULL 02/15] tcg/arm: Add host vector framework Richard Henderson
2021-06-04 20:11 ` [PULL 03/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
2021-06-04 20:11 ` Richard Henderson [this message]
2021-06-04 20:12 ` [PULL 05/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
2021-06-04 20:12 ` [PULL 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
2021-06-04 20:12 ` [PULL 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
2021-06-04 20:12 ` [PULL 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
2021-06-04 20:12 ` [PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-06-04 20:12 ` [PULL 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-06-04 20:12 ` [PULL 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-06-04 20:12 ` [PULL 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-06-04 20:12 ` [PULL 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
2021-06-04 20:12 ` [PULL 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec Richard Henderson
2021-06-04 20:12 ` [PULL 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson
2021-06-05 15:11 ` [PULL 00/15] tcg patch queue Peter Maydell
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