From: Nicolin Chen <nicolinc@nvidia.com>
To: Eric Auger <eric.auger@redhat.com>
Cc: miaoyubo@huawei.com, qemu-arm@nongnu.org, vdumpa@nvidia.com,
qemu-devel@nongnu.org, praithatha@nvidia.com
Subject: Re: [RESEND] Multiple SMMUv3 instances on PCI Bus and PCI Host Bridge
Date: Tue, 8 Jun 2021 22:24:31 -0700 [thread overview]
Message-ID: <20210609052431.GA8835@Asurada-Nvidia> (raw)
In-Reply-To: <a349744d-762b-74b9-352b-ad0a7b16dfec@redhat.com>
Hi Eric,
Thanks for the reply!
On Mon, Jun 07, 2021 at 11:19:39AM +0200, Eric Auger wrote:
> > So I started to have questions in my mind:
> > (1) Can PCI host bridge (PCIE.128) add to a different vSMMU without
> > following PCIE.0's SMMU setup?
> changes need to be made in hw/arm/virt.c
> create_smmu() is passed the primary bus the iommu is attached to.
> Currently arm virt only supports one smmu instance. So playing with qemu
> options is not sufficient.
Yes. I had my local change to do that.
> Besides that, effectively there are IORT changes needed because you need
> to route RCs to the different SMMU instances, ie. some RIDs need to
> reach SMMU#0 and others #SMMU#1.
> You can get inspired of "[PATCH v4 6/8] hw/arm/virt-acpi-build: Add
> explicit IORT idmap for smmuv3 node for this kind of changes."
I see! I tried some change at my IORT table following the way
from this patch. And it seems to work now. Thank you!
prev parent reply other threads:[~2021-06-09 5:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 23:16 [RESEND] Multiple SMMUv3 instances on PCI Bus and PCI Host Bridge Nicolin Chen
2021-06-07 9:19 ` Eric Auger
2021-06-09 5:24 ` Nicolin Chen [this message]
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