From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 26/28] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP
Date: Mon, 14 Jun 2021 01:37:58 -0700 [thread overview]
Message-ID: <20210614083800.1166166-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210614083800.1166166-1-richard.henderson@linaro.org>
Now that the middle-end can replicate the same tricks as tcg/arm
used for optimizing bswap for signed loads and for stores, do not
pretend to have these memory ops in the backend.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 214 ++++++++++++++-------------------------
2 files changed, 77 insertions(+), 139 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 57fd0c0c74..95fcef33bc 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -174,7 +174,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
-#define TCG_TARGET_HAS_MEMORY_BSWAP 1
+#define TCG_TARGET_HAS_MEMORY_BSWAP 0
/* not defined -- call should be eliminated at compile time */
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 9824e215be..35753c9e46 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1366,34 +1366,38 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[8] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
-
- [MO_LEUW] = helper_le_lduw_mmu,
- [MO_LEUL] = helper_le_ldul_mmu,
- [MO_LEQ] = helper_le_ldq_mmu,
- [MO_LESW] = helper_le_ldsw_mmu,
- [MO_LESL] = helper_le_ldul_mmu,
-
- [MO_BEUW] = helper_be_lduw_mmu,
- [MO_BEUL] = helper_be_ldul_mmu,
- [MO_BEQ] = helper_be_ldq_mmu,
- [MO_BESW] = helper_be_ldsw_mmu,
- [MO_BESL] = helper_be_ldul_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_UW] = helper_be_lduw_mmu,
+ [MO_UL] = helper_be_ldul_mmu,
+ [MO_Q] = helper_be_ldq_mmu,
+ [MO_SW] = helper_be_ldsw_mmu,
+ [MO_SL] = helper_be_ldul_mmu,
+#else
+ [MO_UW] = helper_le_lduw_mmu,
+ [MO_UL] = helper_le_ldul_mmu,
+ [MO_Q] = helper_le_ldq_mmu,
+ [MO_SW] = helper_le_ldsw_mmu,
+ [MO_SL] = helper_le_ldul_mmu,
+#endif
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
- [MO_UB] = helper_ret_stb_mmu,
- [MO_LEUW] = helper_le_stw_mmu,
- [MO_LEUL] = helper_le_stl_mmu,
- [MO_LEQ] = helper_le_stq_mmu,
- [MO_BEUW] = helper_be_stw_mmu,
- [MO_BEUL] = helper_be_stl_mmu,
- [MO_BEQ] = helper_be_stq_mmu,
+static void * const qemu_st_helpers[4] = {
+ [MO_8] = helper_ret_stb_mmu,
+#ifdef HOST_WORDS_BIGENDIAN
+ [MO_16] = helper_be_stw_mmu,
+ [MO_32] = helper_be_stl_mmu,
+ [MO_64] = helper_be_stq_mmu,
+#else
+ [MO_16] = helper_le_stw_mmu,
+ [MO_32] = helper_le_stl_mmu,
+ [MO_64] = helper_le_stq_mmu,
+#endif
};
/* Helper routines for marshalling helper function arguments into
@@ -1598,9 +1602,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
icache usage. For pre-armv6, use the signed helpers since we do
not have a single insn sign-extend. */
if (use_armv6_instructions) {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)];
+ func = qemu_ld_helpers[opc & MO_SIZE];
} else {
- func = qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)];
+ func = qemu_ld_helpers[opc & MO_SSIZE];
if (opc & MO_SIGN) {
opc = MO_UL;
}
@@ -1678,7 +1682,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
/* Tail-call to the helper, which will return to the fast path. */
- tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
+ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]);
return true;
}
#endif /* SOFTMMU */
@@ -1687,7 +1691,8 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1698,51 +1703,30 @@ static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
break;
case MO_UW:
tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
break;
case MO_SW:
- if (bswap) {
- tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend);
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OS);
- } else {
- tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
- }
+ tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend);
break;
case MO_UL:
- default:
tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
break;
case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_r(s, COND_AL, dl, addrlo, addend);
- } else if (dl != addend) {
- tcg_out_ld32_rwb(s, COND_AL, dl, addend, addrlo);
- tcg_out_ld32_12(s, COND_AL, dh, addend, 4);
- } else {
- tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
- addend, addrlo, SHIFT_IMM_LSL(0));
- tcg_out_ld32_12(s, COND_AL, dl, TCG_REG_TMP, 0);
- tcg_out_ld32_12(s, COND_AL, dh, TCG_REG_TMP, 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
+ } else if (datalo != addend) {
+ tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
+ tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
+ } else {
+ tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP,
+ addend, addrlo, SHIFT_IMM_LSL(0));
+ tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0);
+ tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1750,7 +1734,8 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SSIZE) {
case MO_UB:
@@ -1761,49 +1746,28 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
break;
case MO_UW:
tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OZ);
- }
break;
case MO_SW:
- if (bswap) {
- tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0);
- tcg_out_bswap16(s, COND_AL, datalo, datalo,
- TCG_BSWAP_IZ | TCG_BSWAP_OS);
- } else {
- tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0);
break;
case MO_UL:
- default:
tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, datalo, datalo);
- }
break;
case MO_Q:
- {
- TCGReg dl = (bswap ? datahi : datalo);
- TCGReg dh = (bswap ? datalo : datahi);
-
- /* Avoid ldrd for user-only emulation, to handle unaligned. */
- if (USING_SOFTMMU && use_armv6_instructions
- && (dl & 1) == 0 && dh == dl + 1) {
- tcg_out_ldrd_8(s, COND_AL, dl, addrlo, 0);
- } else if (dl == addrlo) {
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- } else {
- tcg_out_ld32_12(s, COND_AL, dl, addrlo, bswap ? 4 : 0);
- tcg_out_ld32_12(s, COND_AL, dh, addrlo, bswap ? 0 : 4);
- }
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, dl, dl);
- tcg_out_bswap32(s, COND_AL, dh, dh);
- }
+ /* Avoid ldrd for user-only emulation, to handle unaligned. */
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
+ tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0);
+ } else if (datalo == addrlo) {
+ tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
+ tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
+ } else {
+ tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0);
+ tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1852,44 +1816,31 @@ static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addend)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SIZE) {
case MO_8:
tcg_out_st8_r(s, cond, datalo, addrlo, addend);
break;
case MO_16:
- if (bswap) {
- tcg_out_bswap16(s, cond, TCG_REG_R0, datalo, 0);
- tcg_out_st16_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st16_r(s, cond, datalo, addrlo, addend);
- }
+ tcg_out_st16_r(s, cond, datalo, addrlo, addend);
break;
case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_r(s, cond, TCG_REG_R0, addrlo, addend);
- } else {
- tcg_out_st32_r(s, cond, datalo, addrlo, addend);
- }
+ tcg_out_st32_r(s, cond, datalo, addrlo, addend);
break;
case MO_64:
/* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, cond, TCG_REG_R0, datahi);
- tcg_out_st32_rwb(s, cond, TCG_REG_R0, addend, addrlo);
- tcg_out_bswap32(s, cond, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, cond, TCG_REG_R0, addend, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
tcg_out_strd_r(s, cond, datalo, addrlo, addend);
} else {
tcg_out_st32_rwb(s, cond, datalo, addend, addrlo);
tcg_out_st32_12(s, cond, datahi, addend, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
@@ -1897,44 +1848,31 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo)
{
- MemOp bswap = opc & MO_BSWAP;
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((opc & MO_BSWAP) == 0);
switch (opc & MO_SIZE) {
case MO_8:
tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_16:
- if (bswap) {
- tcg_out_bswap16(s, COND_AL, TCG_REG_R0, datalo, 0);
- tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0);
break;
case MO_32:
- default:
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- } else {
- tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
- }
+ tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
break;
case MO_64:
/* Avoid strd for user-only emulation, to handle unaligned. */
- if (bswap) {
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datahi);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 0);
- tcg_out_bswap32(s, COND_AL, TCG_REG_R0, datalo);
- tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addrlo, 4);
- } else if (USING_SOFTMMU && use_armv6_instructions
- && (datalo & 1) == 0 && datahi == datalo + 1) {
+ if (USING_SOFTMMU && use_armv6_instructions
+ && (datalo & 1) == 0 && datahi == datalo + 1) {
tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0);
} else {
tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0);
tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4);
}
break;
+ default:
+ g_assert_not_reached();
}
}
--
2.25.1
next prev parent reply other threads:[~2021-06-14 8:57 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-14 8:37 [PATCH 00/28] tcg: bswap improvements Richard Henderson
2021-06-14 8:37 ` [PATCH 01/28] tcg: Add flags argument to bswap opcodes Richard Henderson
2021-06-14 9:19 ` Philippe Mathieu-Daudé
2021-06-14 11:49 ` Alex Bennée
2021-06-14 14:43 ` Richard Henderson
2021-06-21 13:41 ` Peter Maydell
2021-06-21 13:51 ` Peter Maydell
2021-06-21 14:02 ` Richard Henderson
2021-06-21 14:15 ` Peter Maydell
2021-06-21 13:59 ` Richard Henderson
2021-06-14 8:37 ` [PATCH 02/28] tcg/i386: Support bswap flags Richard Henderson
2021-06-21 13:53 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 03/28] tcg/aarch64: " Richard Henderson
2021-06-21 14:01 ` Peter Maydell
2021-06-21 14:04 ` Richard Henderson
2021-06-21 18:12 ` Richard Henderson
2021-06-21 19:40 ` Peter Maydell
2021-06-21 19:50 ` Richard Henderson
2021-06-21 19:52 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 04/28] tcg/arm: " Richard Henderson
2021-06-21 14:09 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 05/28] tcg/ppc: Split out tcg_out_ext{8,16,32}s Richard Henderson
2021-06-21 14:18 ` Peter Maydell
2021-06-21 20:44 ` Philippe Mathieu-Daudé
2021-06-14 8:37 ` [PATCH 06/28] tcg/ppc: Split out tcg_out_sari{32,64} Richard Henderson
2021-06-21 14:22 ` Peter Maydell
2021-06-21 14:23 ` Richard Henderson
2021-06-14 8:37 ` [PATCH 07/28] tcg/ppc: Split out tcg_out_bswap16 Richard Henderson
2021-06-21 14:29 ` Peter Maydell
2021-06-21 14:41 ` Richard Henderson
2021-06-14 8:37 ` [PATCH 08/28] tcg/ppc: Split out tcg_out_bswap32 Richard Henderson
2021-06-21 14:30 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 09/28] tcg/ppc: Split out tcg_out_bswap64 Richard Henderson
2021-06-21 14:35 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 10/28] tcg/ppc: Support bswap flags Richard Henderson
2021-06-21 14:38 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 11/28] tcg/ppc: Use power10 byte-reverse instructions Richard Henderson
2021-06-14 8:37 ` [PATCH 12/28] tcg/s390: Support bswap flags Richard Henderson
2021-06-14 8:37 ` [PATCH 13/28] tcg/mips: Support bswap flags in tcg_out_bswap16 Richard Henderson
2021-06-22 6:36 ` Philippe Mathieu-Daudé
2021-06-22 13:54 ` Richard Henderson
2021-06-14 8:37 ` [PATCH 14/28] tcg/mips: Support bswap flags in tcg_out_bswap32 Richard Henderson
2021-06-14 9:31 ` Philippe Mathieu-Daudé
2021-06-14 15:49 ` Richard Henderson
2021-06-14 8:37 ` [PATCH 15/28] tcg/tci: Support bswap flags Richard Henderson
2021-06-14 9:33 ` Philippe Mathieu-Daudé
2021-06-14 8:37 ` [PATCH 16/28] tcg: Handle new bswap flags during optimize Richard Henderson
2021-06-21 14:47 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 17/28] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64 Richard Henderson
2021-06-14 9:41 ` Philippe Mathieu-Daudé
2021-06-14 15:58 ` Richard Henderson
2021-06-22 10:20 ` Philippe Mathieu-Daudé
2021-06-22 13:56 ` Richard Henderson
2021-06-21 15:01 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 18/28] tcg: Make use of bswap flags in tcg_gen_qemu_ld_* Richard Henderson
2021-06-21 15:04 ` Peter Maydell
2021-06-22 6:41 ` Philippe Mathieu-Daudé
2021-06-14 8:37 ` [PATCH 19/28] tcg: Make use of bswap flags in tcg_gen_qemu_st_* Richard Henderson
2021-06-21 15:05 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 20/28] target/arm: Improve REV32 Richard Henderson
2021-06-14 9:08 ` Philippe Mathieu-Daudé
2021-06-21 15:08 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 21/28] target/arm: Improve vector REV Richard Henderson
2021-06-21 15:10 ` Peter Maydell
2021-06-22 6:44 ` Philippe Mathieu-Daudé
2021-06-14 8:37 ` [PATCH 22/28] target/arm: Improve REVSH Richard Henderson
2021-06-14 9:42 ` Philippe Mathieu-Daudé
2021-06-21 15:11 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 23/28] target/i386: Improve bswap translation Richard Henderson
2021-06-21 15:15 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 24/28] target/sh4: Improve swap.b translation Richard Henderson
2021-06-21 15:16 ` Peter Maydell
2021-06-14 8:37 ` [PATCH 25/28] target/mips: Fix gen_mxu_s32ldd_s32lddr Richard Henderson
2021-06-21 20:59 ` Philippe Mathieu-Daudé
2021-06-14 8:37 ` Richard Henderson [this message]
2021-06-21 15:31 ` [PATCH 26/28] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP Peter Maydell
2021-06-14 8:37 ` [PATCH 27/28] tcg/aarch64: " Richard Henderson
2021-06-21 15:33 ` Peter Maydell
2021-06-14 8:38 ` [PATCH 28/28] tcg/riscv: Remove MO_BSWAP handling Richard Henderson
2021-06-18 6:30 ` Alistair Francis
2021-06-14 22:41 ` [PATCH 00/28] tcg: bswap improvements no-reply
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