From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/28] target/arm: Remove fprintf from disas_simd_mod_imm
Date: Tue, 15 Jun 2021 16:43:40 +0100 [thread overview]
Message-ID: <20210615154405.21399-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
The default of this switch is truly unreachable.
The switch selector is 3 bits, and all 8 cases are present.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210604183506.916654-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2477b55c53a..9bb15ca6189 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -8291,7 +8291,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
}
break;
default:
- fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
g_assert_not_reached();
}
--
2.20.1
next prev parent reply other threads:[~2021-06-15 15:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 15:43 [PULL 00/28] target-arm queue Peter Maydell
2021-06-15 15:43 ` [PULL 01/28] hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes Peter Maydell
2021-06-15 15:43 ` [PULL 02/28] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Peter Maydell
2021-06-15 15:43 ` Peter Maydell [this message]
2021-06-15 15:43 ` [PULL 04/28] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Peter Maydell
2021-06-15 15:43 ` [PULL 05/28] hw: virt: consider hw_compat_6_0 Peter Maydell
2021-06-15 15:43 ` [PULL 06/28] hw/arm: add quanta-gbs-bmc machine Peter Maydell
2021-06-15 15:43 ` [PULL 07/28] hw/arm: quanta-gbs-bmc add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment Peter Maydell
2021-06-15 15:43 ` [PULL 09/28] hw/acpi: Provide stub version of acpi_ghes_record_errors() Peter Maydell
2021-06-15 15:43 ` [PULL 10/28] hw/acpi: Provide function acpi_ghes_present() Peter Maydell
2021-06-15 15:43 ` [PULL 11/28] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors Peter Maydell
2021-06-15 15:43 ` [PULL 12/28] target/arm: Fix mte page crossing test Peter Maydell
2021-06-15 15:43 ` [PULL 13/28] hw/arm: gsj add i2c comments Peter Maydell
2021-06-15 15:43 ` [PULL 14/28] hw/arm: gsj add pca9548 Peter Maydell
2021-06-15 15:43 ` [PULL 15/28] hw/arm: quanta-q71l add pca954x muxes Peter Maydell
2021-06-15 15:43 ` [PULL 16/28] target/arm: Provide and use H8 and H1_8 macros Peter Maydell
2021-06-15 15:43 ` [PULL 17/28] target/arm: Enable FPSCR.QC bit for MVE Peter Maydell
2021-06-15 15:43 ` [PULL 18/28] target/arm: Handle VPR semantics in existing code Peter Maydell
2021-06-15 15:43 ` [PULL 19/28] target/arm: Add handling for PSR.ECI/ICI Peter Maydell
2021-06-15 15:43 ` [PULL 20/28] target/arm: Let vfp_access_check() handle late NOCP checks Peter Maydell
2021-06-15 15:43 ` [PULL 21/28] target/arm: Implement MVE LCTP Peter Maydell
2021-06-15 15:43 ` [PULL 22/28] target/arm: Implement MVE WLSTP insn Peter Maydell
2021-06-15 15:44 ` [PULL 23/28] target/arm: Implement MVE DLSTP Peter Maydell
2021-06-15 15:44 ` [PULL 24/28] target/arm: Implement MVE LETP insn Peter Maydell
2021-06-15 15:44 ` [PULL 25/28] target/arm: Add framework for MVE decode Peter Maydell
2021-06-15 15:44 ` [PULL 26/28] target/arm: Move expand_pred_b() data to vec_helper.c Peter Maydell
2021-06-15 15:44 ` [PULL 27/28] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Peter Maydell
2021-06-15 15:44 ` [PULL 28/28] include/qemu/int128.h: Add function to create Int128 from int64_t Peter Maydell
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