[PATCH v3 00/44] target/arm: First slice of MVE implementation

[Peter Maydell <peter.maydell@linaro.org>]

This is the remainder of the MVE patches (a dozen or so are already
in git). All reviewed, except patches 1 and 2.

Changes v2->v3:
 * patches 1 and 2: pass MSIZE into DO_VLDR/DO_VSTR macros,
   so we increment the address by the correct amount for the
   widening/narrowing accesses. Increment the address outside
   the "only if predicated" condition.
 * patch 9: used the header file and renamed to tcg_gen_dup*.
   I also added in a tcg_gen_dup_tl #define.

thanks
-- PMM

Peter Maydell (44):
  target/arm: Implement MVE VLDR/VSTR (non-widening forms)
  target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
  target/arm: Implement MVE VCLZ
  target/arm: Implement MVE VCLS
  target/arm: Implement MVE VREV16, VREV32, VREV64
  target/arm: Implement MVE VMVN (register)
  target/arm: Implement MVE VABS
  target/arm: Implement MVE VNEG
  tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
  target/arm: Implement MVE VDUP
  target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
  target/arm: Implement MVE VADD, VSUB, VMUL
  target/arm: Implement MVE VMULH
  target/arm: Implement MVE VRMULH
  target/arm: Implement MVE VMAX, VMIN
  target/arm: Implement MVE VABD
  target/arm: Implement MVE VHADD, VHSUB
  target/arm: Implement MVE VMULL
  target/arm: Implement MVE VMLALDAV
  target/arm: Implement MVE VMLSLDAV
  target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
  target/arm: Implement MVE VADD (scalar)
  target/arm: Implement MVE VSUB, VMUL (scalar)
  target/arm: Implement MVE VHADD, VHSUB (scalar)
  target/arm: Implement MVE VBRSR
  target/arm: Implement MVE VPST
  target/arm: Implement MVE VQADD and VQSUB
  target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
  target/arm: Implement MVE VQDMULL scalar
  target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
  target/arm: Implement MVE VQADD, VQSUB (vector)
  target/arm: Implement MVE VQSHL (vector)
  target/arm: Implement MVE VQRSHL
  target/arm: Implement MVE VSHL insn
  target/arm: Implmement MVE VRSHL
  target/arm: Implement MVE VQDMLADH and VQRDMLADH
  target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
  target/arm: Implement MVE VQDMULL (vector)
  target/arm: Implement MVE VRHADD
  target/arm: Implement MVE VADC, VSBC
  target/arm: Implement MVE VCADD
  target/arm: Implement MVE VHCADD
  target/arm: Implement MVE VADDV
  target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

 include/tcg/tcg-op.h       |    8 +
 include/tcg/tcg.h          |    1 -
 target/arm/helper-mve.h    |  357 +++++++++++
 target/arm/helper.h        |    2 +
 target/arm/internals.h     |   11 +
 target/arm/translate-a32.h |    2 +
 target/arm/translate.h     |   10 +
 target/arm/mve.decode      |  240 ++++++++
 target/arm/mve_helper.c    | 1175 ++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  759 +++++++++++++++++++++++
 target/arm/translate-vfp.c |   77 ++-
 tcg/tcg-op-gvec.c          |   20 +-
 target/arm/meson.build     |    1 +
 13 files changed, 2646 insertions(+), 17 deletions(-)
 create mode 100644 target/arm/helper-mve.h
 create mode 100644 target/arm/mve_helper.c

-- 
2.20.1