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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 18/44] target/arm: Implement MVE VMULL
Date: Thu, 17 Jun 2021 13:16:02 +0100	[thread overview]
Message-ID: <20210617121628.20116-19-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210617121628.20116-1-peter.maydell@linaro.org>

Implement the MVE VMULL insn, which multiplies two single
width integer elements to produce a double width result.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper-mve.h    | 14 ++++++++++++++
 target/arm/mve.decode      |  5 +++++
 target/arm/mve_helper.c    | 34 ++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  4 ++++
 4 files changed, 57 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 02bef53ed41..9bbeb7ec49d 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -130,3 +130,17 @@ DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vmullbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmullbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmullbsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmullbub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmullbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmullbuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vmulltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmulltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 241d1c44c19..5a480d61cd6 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -101,6 +101,11 @@ VHADD_U          111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op
 VHSUB_S          111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
 VHSUB_U          111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
 
+VMULL_BS         111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
+VMULL_BU         111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
+VMULL_TS         111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
+VMULL_TU         111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
+
 # Vector miscellaneous
 
 VCLS             1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index a89f6e3b01b..4bb4b6ce02e 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -364,6 +364,26 @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
     DO_2OP(OP##h, 2, int16_t, FN)               \
     DO_2OP(OP##w, 4, int32_t, FN)
 
+/*
+ * "Long" operations where two half-sized inputs (taken from either the
+ * top or the bottom of the input vector) produce a double-width result.
+ * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output.
+ */
+#define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)               \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *n = vn, *m = vm;                                          \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)],              \
+                         m[H##ESIZE(le * 2 + TOP)]);                    \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
 #define DO_AND(N, M)  ((N) & (M))
 #define DO_BIC(N, M)  ((N) & ~(M))
 #define DO_ORR(N, M)  ((N) | (M))
@@ -384,6 +404,20 @@ DO_2OP_U(vadd, DO_ADD)
 DO_2OP_U(vsub, DO_SUB)
 DO_2OP_U(vmul, DO_MUL)
 
+DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL)
+DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL)
+DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL)
+DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL)
+DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL)
+DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL)
+
+DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL)
+DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL)
+DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL)
+DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL)
+DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL)
+DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL)
+
 /*
  * Because the computation type is at least twice as large as required,
  * these work for both signed and unsigned source types.
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index f593d3693b9..1cadc3b04da 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -361,3 +361,7 @@ DO_2OP(VHADD_S, vhadds)
 DO_2OP(VHADD_U, vhaddu)
 DO_2OP(VHSUB_S, vhsubs)
 DO_2OP(VHSUB_U, vhsubu)
+DO_2OP(VMULL_BS, vmullbs)
+DO_2OP(VMULL_BU, vmullbu)
+DO_2OP(VMULL_TS, vmullts)
+DO_2OP(VMULL_TU, vmulltu)
-- 
2.20.1



  parent reply	other threads:[~2021-06-17 12:36 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-17 12:15 [PATCH v3 00/44] target/arm: First slice of MVE implementation Peter Maydell
2021-06-17 12:15 ` [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-17 13:30   ` Claudio Fontana
2021-06-17 13:47     ` Peter Maydell
2021-06-18 14:44   ` Richard Henderson
2021-06-17 12:15 ` [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Peter Maydell
2021-06-18 14:47   ` Richard Henderson
2021-06-17 12:15 ` [PATCH v3 03/44] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-21 13:28   ` Peter Maydell
2021-06-21 16:12   ` Peter Maydell
2021-06-17 12:15 ` [PATCH v3 04/44] target/arm: Implement MVE VCLS Peter Maydell
2021-06-17 12:15 ` [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-17 12:15 ` [PATCH v3 06/44] target/arm: Implement MVE VMVN (register) Peter Maydell
2021-06-17 12:15 ` [PATCH v3 07/44] target/arm: Implement MVE VABS Peter Maydell
2021-06-17 12:15 ` [PATCH v3 08/44] target/arm: Implement MVE VNEG Peter Maydell
2021-06-17 12:15 ` [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 Peter Maydell
2021-06-17 12:15 ` [PATCH v3 10/44] target/arm: Implement MVE VDUP Peter Maydell
2021-06-17 12:15 ` [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-17 12:15 ` [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-17 12:15 ` [PATCH v3 13/44] target/arm: Implement MVE VMULH Peter Maydell
2021-06-17 12:15 ` [PATCH v3 14/44] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-17 12:15 ` [PATCH v3 15/44] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-17 12:16 ` [PATCH v3 16/44] target/arm: Implement MVE VABD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 17/44] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-17 12:16 ` Peter Maydell [this message]
2021-06-17 12:16 ` [PATCH v3 19/44] target/arm: Implement MVE VMLALDAV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 21/44] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-17 12:16 ` [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 24/44] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 25/44] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-17 12:16 ` [PATCH v3 26/44] target/arm: Implement MVE VPST Peter Maydell
2021-06-17 12:16 ` [PATCH v3 27/44] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-17 12:16 ` [PATCH v3 28/44] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 29/44] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-17 12:16 ` [PATCH v3 30/44] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 32/44] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 33/44] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-17 12:16 ` [PATCH v3 34/44] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-17 12:16 ` [PATCH v3 35/44] target/arm: Implmement MVE VRSHL Peter Maydell
2021-06-17 13:20   ` Claudio Fontana
2021-06-17 13:23     ` Peter Maydell
2021-06-17 12:16 ` [PATCH v3 36/44] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-17 12:16 ` [PATCH v3 37/44] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Peter Maydell
2021-06-17 12:16 ` [PATCH v3 38/44] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 39/44] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 40/44] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-17 12:16 ` [PATCH v3 41/44] target/arm: Implement MVE VCADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 42/44] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 43/44] target/arm: Implement MVE VADDV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 44/44] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-17 13:10 ` [PATCH v3 00/44] target/arm: First slice of MVE implementation no-reply

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