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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 37/44] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Date: Thu, 17 Jun 2021 13:16:21 +0100	[thread overview]
Message-ID: <20210617121628.20116-38-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210617121628.20116-1-peter.maydell@linaro.org>

Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are
like VQDMLADH and VQRDMLADH except that products are subtracted
rather than added.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper-mve.h    | 16 ++++++++++++++
 target/arm/mve.decode      |  5 +++++
 target/arm/mve_helper.c    | 44 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  4 ++++
 4 files changed, 69 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index c3cc6a08476..61f8082e0e3 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -217,6 +217,22 @@ DEF_HELPER_FLAGS_4(mve_vqrdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vqrdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 DEF_HELPER_FLAGS_4(mve_vqrdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
 
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
 DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index d267c8838eb..fa4fb1b2038 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -147,6 +147,11 @@ VQDMLADHX        1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op
 VQRDMLADH        1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op
 VQRDMLADHX       1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op
 
+VQDMLSDH         1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op
+VQDMLSDHX        1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op
+VQRDMLSDH        1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op
+VQRDMLSDHX       1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op
+
 # Vector miscellaneous
 
 VCLS             1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 9c64e4979bc..8db03003ce1 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -717,6 +717,36 @@ static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d,
     return r >> 32;
 }
 
+static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d,
+                            int round, bool *sat)
+{
+    int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7);
+    return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8;
+}
+
+static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d,
+                             int round, bool *sat)
+{
+    int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15);
+    return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16;
+}
+
+static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d,
+                             int round, bool *sat)
+{
+    int64_t m1 = (int64_t)a * b;
+    int64_t m2 = (int64_t)c * d;
+    int64_t r;
+    /* The same ordering issue as in do_vqdmladh_w applies here too */
+    if (ssub64_overflow(m1, m2, &r) ||
+        sadd64_overflow(r, (round << 30), &r) ||
+        sadd64_overflow(r, r, &r)) {
+        *sat = true;
+        return r < 0 ? INT32_MAX : INT32_MIN;
+    }
+    return r >> 32;
+}
+
 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b)
 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h)
 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w)
@@ -731,6 +761,20 @@ DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b)
 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h)
 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w)
 
+DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b)
+DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h)
+DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w)
+DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b)
+DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h)
+DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w)
+
+DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b)
+DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h)
+DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w)
+DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b)
+DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h)
+DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w)
+
 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN)                              \
     void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn,   \
                                 uint32_t rm)                            \
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index d830b42d5ce..27b3e378ac7 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -414,6 +414,10 @@ DO_2OP(VQDMLADH, vqdmladh)
 DO_2OP(VQDMLADHX, vqdmladhx)
 DO_2OP(VQRDMLADH, vqrdmladh)
 DO_2OP(VQRDMLADHX, vqrdmladhx)
+DO_2OP(VQDMLSDH, vqdmlsdh)
+DO_2OP(VQDMLSDHX, vqdmlsdhx)
+DO_2OP(VQRDMLSDH, vqrdmlsdh)
+DO_2OP(VQRDMLSDHX, vqrdmlsdhx)
 
 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
                           MVEGenTwoOpScalarFn fn)
-- 
2.20.1



  parent reply	other threads:[~2021-06-17 12:53 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-17 12:15 [PATCH v3 00/44] target/arm: First slice of MVE implementation Peter Maydell
2021-06-17 12:15 ` [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Peter Maydell
2021-06-17 13:30   ` Claudio Fontana
2021-06-17 13:47     ` Peter Maydell
2021-06-18 14:44   ` Richard Henderson
2021-06-17 12:15 ` [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Peter Maydell
2021-06-18 14:47   ` Richard Henderson
2021-06-17 12:15 ` [PATCH v3 03/44] target/arm: Implement MVE VCLZ Peter Maydell
2021-06-21 13:28   ` Peter Maydell
2021-06-21 16:12   ` Peter Maydell
2021-06-17 12:15 ` [PATCH v3 04/44] target/arm: Implement MVE VCLS Peter Maydell
2021-06-17 12:15 ` [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64 Peter Maydell
2021-06-17 12:15 ` [PATCH v3 06/44] target/arm: Implement MVE VMVN (register) Peter Maydell
2021-06-17 12:15 ` [PATCH v3 07/44] target/arm: Implement MVE VABS Peter Maydell
2021-06-17 12:15 ` [PATCH v3 08/44] target/arm: Implement MVE VNEG Peter Maydell
2021-06-17 12:15 ` [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 Peter Maydell
2021-06-17 12:15 ` [PATCH v3 10/44] target/arm: Implement MVE VDUP Peter Maydell
2021-06-17 12:15 ` [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Peter Maydell
2021-06-17 12:15 ` [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL Peter Maydell
2021-06-17 12:15 ` [PATCH v3 13/44] target/arm: Implement MVE VMULH Peter Maydell
2021-06-17 12:15 ` [PATCH v3 14/44] target/arm: Implement MVE VRMULH Peter Maydell
2021-06-17 12:15 ` [PATCH v3 15/44] target/arm: Implement MVE VMAX, VMIN Peter Maydell
2021-06-17 12:16 ` [PATCH v3 16/44] target/arm: Implement MVE VABD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 17/44] target/arm: Implement MVE VHADD, VHSUB Peter Maydell
2021-06-17 12:16 ` [PATCH v3 18/44] target/arm: Implement MVE VMULL Peter Maydell
2021-06-17 12:16 ` [PATCH v3 19/44] target/arm: Implement MVE VMLALDAV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 21/44] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Peter Maydell
2021-06-17 12:16 ` [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 24/44] target/arm: Implement MVE VHADD, VHSUB (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 25/44] target/arm: Implement MVE VBRSR Peter Maydell
2021-06-17 12:16 ` [PATCH v3 26/44] target/arm: Implement MVE VPST Peter Maydell
2021-06-17 12:16 ` [PATCH v3 27/44] target/arm: Implement MVE VQADD and VQSUB Peter Maydell
2021-06-17 12:16 ` [PATCH v3 28/44] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 29/44] target/arm: Implement MVE VQDMULL scalar Peter Maydell
2021-06-17 12:16 ` [PATCH v3 30/44] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 32/44] target/arm: Implement MVE VQSHL (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 33/44] target/arm: Implement MVE VQRSHL Peter Maydell
2021-06-17 12:16 ` [PATCH v3 34/44] target/arm: Implement MVE VSHL insn Peter Maydell
2021-06-17 12:16 ` [PATCH v3 35/44] target/arm: Implmement MVE VRSHL Peter Maydell
2021-06-17 13:20   ` Claudio Fontana
2021-06-17 13:23     ` Peter Maydell
2021-06-17 12:16 ` [PATCH v3 36/44] target/arm: Implement MVE VQDMLADH and VQRDMLADH Peter Maydell
2021-06-17 12:16 ` Peter Maydell [this message]
2021-06-17 12:16 ` [PATCH v3 38/44] target/arm: Implement MVE VQDMULL (vector) Peter Maydell
2021-06-17 12:16 ` [PATCH v3 39/44] target/arm: Implement MVE VRHADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 40/44] target/arm: Implement MVE VADC, VSBC Peter Maydell
2021-06-17 12:16 ` [PATCH v3 41/44] target/arm: Implement MVE VCADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 42/44] target/arm: Implement MVE VHCADD Peter Maydell
2021-06-17 12:16 ` [PATCH v3 43/44] target/arm: Implement MVE VADDV Peter Maydell
2021-06-17 12:16 ` [PATCH v3 44/44] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Peter Maydell
2021-06-17 13:10 ` [PATCH v3 00/44] target/arm: First slice of MVE implementation no-reply

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