[PATCH 4/4] target/mips: Add declarations for generic DSP TCG helpers

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

To be able to extract the DSP ASE translation routines to
different source file, declare few TCG helpers, MASK_SPECIAL3
and a DSP register in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.h |  7 +++++++
 target/mips/tcg/translate.c | 10 +++++-----
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index c25fad597d5..c6f57de7e0d 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -52,6 +52,8 @@ typedef struct DisasContext {
 /* MIPS major opcodes */
 #define MASK_OP_MAJOR(op)   (op & (0x3F << 26))
 
+#define MASK_SPECIAL3(op)   (MASK_OP_MAJOR(op) | (op & 0x3F))
+
 #define OPC_CP1 (0x11 << 26)
 
 /* Coprocessor 1 (rs field) */
@@ -131,6 +133,10 @@ void check_cp1_64bitmode(DisasContext *ctx);
 void check_cp1_registers(DisasContext *ctx, int regs);
 void check_cop1x(DisasContext *ctx);
 
+void check_dsp(DisasContext *ctx);
+void check_dsp_r2(DisasContext *ctx);
+void check_dsp_r3(DisasContext *ctx);
+
 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
 void gen_move_low32(TCGv ret, TCGv_i64 arg);
 void gen_move_high32(TCGv ret, TCGv_i64 arg);
@@ -168,6 +174,7 @@ extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 extern TCGv_i64 fpu_f64[32];
 extern TCGv bcond;
+extern TCGv cpu_dspctrl;
 
 #define LOG_DISAS(...)                                                        \
     do {                                                                      \
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 7b173e2bd2f..97ef816e95f 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -374,7 +374,6 @@ enum {
 };
 
 /* Special3 opcodes */
-#define MASK_SPECIAL3(op)           (MASK_OP_MAJOR(op) | (op & 0x3F))
 
 enum {
     OPC_EXT      = 0x00 | OPC_SPECIAL3,
@@ -1227,8 +1226,9 @@ TCGv cpu_gpr[32], cpu_PC;
  */
 TCGv_i64 cpu_gpr_hi[32];
 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget;
+static TCGv btarget;
 TCGv bcond;
+TCGv cpu_dspctrl;
 static TCGv cpu_lladdr, cpu_llval;
 static TCGv_i32 hflags;
 TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -1633,7 +1633,7 @@ void check_cp1_registers(DisasContext *ctx, int regs)
  * Verify that the processor is running with DSP instructions enabled.
  * This is enabled by CP0 Status register MX(24) bit.
  */
-static inline void check_dsp(DisasContext *ctx)
+void check_dsp(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
         if (ctx->insn_flags & ASE_DSP) {
@@ -1644,7 +1644,7 @@ static inline void check_dsp(DisasContext *ctx)
     }
 }
 
-static inline void check_dsp_r2(DisasContext *ctx)
+void check_dsp_r2(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
         if (ctx->insn_flags & ASE_DSP) {
@@ -1655,7 +1655,7 @@ static inline void check_dsp_r2(DisasContext *ctx)
     }
 }
 
-static inline void check_dsp_r3(DisasContext *ctx)
+void check_dsp_r3(DisasContext *ctx)
 {
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
         if (ctx->insn_flags & ASE_DSP) {
-- 
2.31.1